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copyright ? cirrus logic, inc. 2007 (all rights reserved) http://www.cirrus.com 192 khz digital audio interface receiver features ? complete eiaj cp1201, iec-60958, aes3, s/pdif-compatible receiver ? +3.3 v analog supply (va) ? +3.3 v digital supply (vd) ? +3.3 v or +5.0 v digital interface supply (vl) ? 8:2 s/pdif input mux ? aes/spdif input pins selectable in hardware mode ? three general purpose outputs (gpo) allow signal routing ? selectable signal routing to gpo pins ? s/pdif-to-tx inputs selectable in hardware mode ? flexible 3-wire serial digital output port ? 32 khz to 192 khz sample frequency range ? low-jitter clock recovery ? pin and microcontroller read access to channel status and user data ? spi? or i2c ? control port software mode and stand-alone hardware mode ? differential cable receiver ? on-chip channel status data buffer memories ? auto-detection of compressed audio input streams ? decodes cd q sub-code ? omck system clock mode see the general description and ordering information on page 2 . clock & data recovery misc. control serial audio output receiver aes3 s/pdif decoder control port & registers rxn rxp1 olrck osclk sdout rst sda/ cdout scl/ cclk ad1/ cdin ad0/ cs agnd filt vl dgnd rmck rxp2 rxp3 rxp4 rxp5 rxp6 rxp7 8:2 mux omck gpo0 gpo1 ad2/gpo2 rxp0 n:3 mux vd va tx passthrough format detect c & u bit data buffer de-emphasis filter august '07 ds578f3 cs8416
2 ds578f3 cs8416 general description the cs8416 is a monolithic cmos device that receives and decodes one of eight stereo pairs of digital audio data according to the iec60958, s/pdif, eiaj cp1201, or aes3 interface standards . the cs8416 has a serial digital audio output port and comprehensive control ability th rough a selectable control port in software mode or through selectable pins in hardware mode. channel status data ar e assembled in buffers, making read access easy. gpo pins may be assigned to route a variety of signals to output pins. a low-jitter clock recovery mechanis m yields a very clean recovered cl ock from the incoming aes3 stream. stand-alone operation allows systems with no microcontrolle r to operate the cs8416 with dedicated output pins for channel status data. the cs8416 is available in 28-pin tssop, soic, and qf n packages in commercial grade (-10 to +70 c) and automotive grade (-40 to +85 c). the cdb8416 customer demonstration board is also available for device eval- uation and implementation suggestions. please refer to ?ordering information? on page 59 for complete ordering information. target applications include a/v receiv ers, cd-r, dvd receivers, multimedia speakers, digital mixing consoles, ef- fects processors, set-top boxes, and computer and automotive audio systems.
ds578f3 3 cs8416 table of contents 1. characteristics and specifications ..................................................................................... 6 specified operating conditions ............................................................................................... 6 absolute maximum ratings ....................................................................................................... .. 6 dc electrical characteristics................................................................................................. 7 digital input characteristics .................................................................................................. .7 digital interface specifications.............................................................................................. 7 switching characteristics ...................................................................................................... .. 8 switching characteristics - serial audio ports............................................................... 9 switching characteristics - control port - spi mode .................................................. 10 switching characteristics - control port- i2c format ............................................... 11 2. pin description - software mode .......................................................................................... 1 2 2.1 tssop pin description ..................................................................................................... ............ 12 2.2 qfn pin description ....................................................................................................... ............... 14 3. pin description - hardware mode ......................................................................................... 16 3.1 tssop pin description ..................................................................................................... ............ 16 3.2 qfn pin description ....................................................................................................... ............... 18 4. typical connection diagrams ............................................................................................... .20 5. applications .............................................................................................................. .................... 22 5.1 reset, power-down and start-up ............................................................................................ ..... 22 5.2 id code and revision code ................................................................................................. ......... 22 5.3 power supply, grounding, and pcb layout ................................................................................. 22 6. general description ....................................................................................................... ........... 23 6.1 aes3 and s/pdif standards documents ..................................................................................... 23 7. serial audio output port .................................................................................................. ....... 23 7.1 slip/repeat behavior ...................................................................................................... ............... 25 7.2 aes11 behavior ............................................................................................................ ................ 26 8. s/pdif receiver ........................................................................................................... ................... 27 8.1 8:2 s/pdif input multiplexer .............................................................................................. ........... 27 8.1.1 general ................................................................................................................. .............. 27 8.1.2 software mode ........................................................................................................... ........ 27 8.1.3 hardware mode ........................................................................................................... ....... 28 8.2 omck system clock mode .................................................................................................... ....... 28 8.3 clock recovery and pll filter ................... .......................................................................... ......... 28 9. general purpose outputs ................................................................................................... .... 29 10. error and status reporting ...................... ......................................................................... .30 10.1 general .................................................................................................................. ...................... 30 10.1.1 software mode .......................................................................................................... ....... 30 10.1.2 hardware mode ......... ................................................................................................. ...... 30 10.2 non-audio detection ...................................................................................................... ............. 31 10.2.1 format detection ....... ................................................................................................ ....... 31 10.3 interrupts ................. .............................................................................................. ...................... 31 11. channel status and user-data handling ....................................................................... 32 11.1 software mode ............................................................................................................ ................ 32 11.2 hardware mode . ........................................................................................................... ............... 32 12. control port description ................................................................................................. .... 33 12.1 spi mode ................................................................................................................. .................... 33 12.2 i2c mode ................................................................................................................. ..................... 34 13. control port register quick reference . ...................................................................... 35 14. control port register descriptions .............................................................................. 36 14.1 memory address pointer (m ap) ............................................................................................. ..... 36 14.2 control0 (00h) ........................................................................................................... .................. 36 14.3 control1 (01h) ........................................................................................................... .................. 37
4 ds578f3 cs8416 14.4 control2 (02h) ........................................................................................................... .................. 38 14.5 control3 (03h) ........................................................................................................... .................. 39 14.6 control4 (04h) ........................................................................................................... .................. 39 14.7 serial audio data format (05h) ........................................................................................... ........ 40 14.8 receiver error mask (06h) ...................... ......................................................................... .......... 41 14.9 interrupt mask (07h) ..................................................................................................... ............... 41 14.10 interrupt mode msb (08h) and interrup t mode lsb(09h) ......................................................... 41 14.11 receiver channel status (0ah) .......................................................................................... ...... 42 14.12 format detect status (0bh) .............................................................................................. ......... 42 14.13 receiver error (0ch) ................................................................................................... ............. 43 14.14 interrupt 1 status (0dh) ............................................................................................... ............. 44 14.15 q-channel subcode (0eh - 17h) ........................................................................................... .... 44 14.16 omck/rmck ratio (18h) ................................................................................................. ...... 45 14.17 channel status registers (19h - 22h) .................................................................................... ... 45 14.18 iec61937 pc/pd burs t preamble (23h - 26h) .......................................................................... 45 14.19 cs8416 i.d. and version register (7fh) .................................................................................. .45 15. hardware mode ............................................................................................................ .............. 46 15.1 serial audio port formats ................................................................................................ ........... 46 15.2 hardware mode fu nction selection ......................................................................................... ... 46 15.3 hardware mode equivalent register settings ............................................................................. 47 16. external aes3/spdif/iec60958 receiver components ................................................... 49 16.1 aes3 receiver external comp onents ........................................................................................ 49 16.2 isolating transformer requirements ....................................................................................... .... 49 17. channel status buffer management ............................................................................... 51 17.1 aes3 channel status (c) bit management ................................................................................ 51 17.2 accessing the e buffer ................................................................................................... ............. 51 17.2.1 serial copy management system (scms) ...................................................................... 51 18. pll filter ............................................................................................................... ........................ 53 18.1 general .................................................................................................................. ...................... 53 18.2 external filter components ............................................................................................... .......... 53 18.2.1 general ................................................................................................................ ............. 53 18.2.2 capacitor selection .................................................................................................... ...... 54 18.2.3 circuit board layout ................................................................................................... ...... 54 18.2.4 component value selection ............................................................................................. 5 4 18.2.5 jitter attenuation ..................................................................................................... .......... 55 19. package dimensions ....................................................................................................... .......... 56 tssop thermal characteristics............................................................................................. 57 qfn thermal characteristics ................................................................................................. 58 20. ordering information ..................................................................................................... ........ 59 21. revision history ......................................................................................................... ................ 60
ds578f3 5 cs8416 list of figures figure 1. audio port master mode timing ........................................................................................ ........... 9 figure 2. audio port slave mode and data input timing.......................................................................... ... 9 figure 3. spi mode timing ...................................................................................................... .................. 10 figure 4. i2c mode timing ...................................................................................................... ................... 11 figure 5. typical connection diagram - software mode ........................................................................... 20 figure 6. typical connection diagr am - hardware mode .......................................................................... 2 1 figure 7. serial audio output example formats..... ............................................................................. ...... 24 figure 8. aes3 data format..................................................................................................... ................. 25 figure 9. receiver input structure ............................................................................................. ................ 27 figure 10. c/u data outputs.................................................................................................... .................. 32 figure 11. control port timing in spi mode ..................................................................................... ......... 33 figure 12. control port timing, i2c slave mode write........................................................................... .... 34 figure 13. control port timing, i2c slave mode read............................................................................ ... 34 figure 14. de-emphasis filter response ......................................................................................... ......... 39 figure 15. hardware mode data flow ............................................................................................. .......... 46 figure 16. professional input circuit .......................................................................................... ................ 49 figure 17. transformerless professional input circuit .......................................................................... ..... 49 figure 18. consumer input circuit .............................................................................................. ............... 50 figure 19. s/pdif mux input circuit ............................................................................................ ............. 50 figure 20. ttl/cmos input circuit.............................................................................................. .............. 50 figure 21. channel status data buffer structure................................................................................ ....... 52 figure 22. flowchart for reading the e buffer.................................................................................. ......... 52 figure 23. pll block diagram ................................................................................................... ................ 53 figure 24. recomm ended layout example.......................................................................................... ..... 54 figure 25. jitter attenuation characteristics of pll........................................................................... ........ 55 list of tables table 1. typical delays by frequency values .................................................................................... ....... 26 table 2. clock switching output clock rates..... ............................................................................... ........ 28 table 3. gpo pin configurations................................................................................................ ............... 29 table 4. hardware mode start-up pin conditions ................................................................................. .... 47 table 5. hardware mode serial audio format select.............................................................................. .. 48 table 6. external pll component values ......................................................................................... ........ 54
6 ds578f3 cs8416 1. characteristics and specifications all min/max characteristics and specif ications are guaranteed over the spec ified operating conditions. typical performance characteristics and specifications are derive d from measurements taken at nominal supply voltages and t a = 25c. specified operating conditions (agnd, dgnd = 0 v, all voltages with respect to 0 v) absolute maximum ratings (agnd, dgnd = 0 v; all voltages with respect to 0 v. op eration beyond these limits may result in permanent dam- age to the device. normal operation is not guaranteed at these extremes.) notes: 1. transient currents of up to 10 0 ma will not caus e scr latch-up. parameter symbol min typ max units power supply voltage va vd vl 3.13 3.13 3.13 3.3 3.3 3.3 or 5.0 3.46 3.46 5.25 v v v ambient operating temper ature: commercial grade automotive grade t a -10 -40 - - +70 +85 c parameter symbol min max units power supply voltage va, vd,vl - 6.0 v input current, any pin except supplies (note 1) i in -10ma input voltage v in -0.3 (vl) + 0.3 v ambient operating temper ature (power applied) t a -55 125 c storage temperature t stg -65 150 c
ds578f3 7 cs8416 dc electrical characteristics (agnd = dgnd = 0 v; all voltages with respect to 0 v.) notes: 2. power-down mode is defined as rst = lo with all clocks and data lines held static. 3. normal operation is defined as rst = hi. 4. assumes that no inputs are floating. it is recommended that all inputs be driven high or low at all times. digital input characteristics (agnd = dgnd = 0 v; all voltages with respect to 0 v.) digital interface specifications (agnd = dgnd = 0 v; all voltages with respect to 0 v.) parameters symbol min typ max units power-down mode (notes 2, 4) supply current in power-down va vd vl = 3.3 v vl = 5.0 v ia id il il - - - - 10 70 10 12 - - - - a a a a normal operation (notes 3, 4) supply current at 48 khz frame rate va vd vl = 3.3 v vl = 5.0 v ia id il il - - - - 5.7 5.9 2.8 4.2 - - - - ma ma ma ma supply current at 192 khz frame rate va vd vl = 3.3 v vl = 5.0 v ia id il il - - - - 9.4 23 7.8 11.8 - - - - ma ma ma ma parameters symbol min typ max units input leakage current i in --0.5 a differential input sensit ivity, rxp[7:0] to rxn v th - 150 200 mvpp input hysteresis v h 0.15 - 1.0 v parameters symbol min max units high-level output voltage (i oh = -3.2 ma) v oh (vl) - 1.0 - v low-level output voltage (i ol = 3.2 ma) v ol -0.5v high-level input voltage, except rxp[7:0], rxn v ih 2.0 (vl) + 0.3 v low-level input voltage, except rxp[7:0], rxn v il -0.3 0.8 v
8 ds578f3 cs8416 switching characteristics (inputs: logic 0 = 0 v, logic 1 = vl; c l = 20 pf) notes: 5. typical rms cycle-to-cycle jitter. 6. duty cycle when clock is recovered from biphase encoded input. 7. duty cycle when omck is swit ched over for output on rmck. parameter symbol min typ max units rst pin low pulse width 200 - - s pll clock recovery sample rate range 30 - 200 khz rmck output jitter (note 5) -200-ps rms rmck output duty-cycle (note 6) (note 7) 45 50 50 55 55 65 % % rmck/omck maximum frequency - - 50 mhz
ds578f3 9 cs8416 switching characteristics - serial audio ports (inputs: logic 0 = 0 v, logic 1 = vl; c l = 20 pf) notes: 8. in software mode the active edges of osclk are programmable. 9. in software mode the polari ty of olrck is programmable. 10. this delay is to prevent the previous osclk edge from being interpreted as the first one after olrck has changed. 11. this setup time ensures that this osclk edge is interpreted as the first one after olrck has changed. parameter symbol min typ max units osclk/olrck active edge to sdout output valid (note 8) t dpd --23ns master mode rmck to osclk active edge delay (note 8) t smd 0-12ns rmck to olrck delay (note 9) t lmd 0-12ns osclk and olrck duty cycle - 50 - % slave mode osclk period t sckw 36 - - ns osclk input low width t sckl 14 - - ns osclk input high width t sckh 14 - - ns osclk active edge to olrck edge (notes 8,9,10) t lrckd 10 - - ns osclk edge setup before osclk active-edge (notes 8,9,11) t lrcks 10 - - ns figure 1. audio port master mode timing figure 2. audio po rt slave mode and data input sckh sckl sckw t t t t dpd sdout (input) (input) lrcks t lrckd t osclk olrck t smd t lm d osclk (output) olrck (output) rmck (output)
10 ds578f3 cs8416 switching characteristics - control port - spi mode (inputs: logic 0 = 0 v, logic 1 = vl; c l = 20 pf) notes: 12. if fs is lower than 46.875 khz, the maximum cclk frequency should be less than 128 fs. this is dic- tated by the timing requirements necessary to access the channel status memory. access to the con- trol register file can be carried out at the full 6 m hz rate. the minimum allowable input sample rate is 32 khz, so choosing cclk to be less than or equal to 4.1 mhz should be safe for all possible conditions. 13. data must be held for sufficient time to bridge the transition time of cclk. 14. for f sck <1 mhz. parameter symbol min max unit cclk clock frequency (note 12) f sck 06.0mhz cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 13) t dh 15 - ns cclk falling to cdout stable t pd -50ns rise time of cdout t r1 -25ns fall time of cdout t f1 -25ns rise time of cclk and cdin (note 14) t r2 -100ns fall time of cclk and cdin (note 14) t r2 -100ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t pd cdout t csh figure 3. spi mode timing
ds578f3 11 cs8416 switching characteristics - control port- i2c format (inputs: logic 0 = 0 v, logic 1 = vl; c l = 20 pf) notes: 15. data must be held for sufficient time to bridge the 300 ns transition time of scl. parameter symbol min max unit scl clock frequency f scl -100khz bus free time between transmissions t buf 4.7 - s start condition hold time (p rior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 15) t hdd 10 - ns sda setup time to scl rising t sud 250 - ns rise time of scl and sda t r - 1000 ns fall time scl and sda t f -300ns setup time for stop condition t susp 4.7 - s t buf t hdst t hdst t low t r t f t hdd t high t sud t sust t susp stop start start stop repeated sda scl figure 4. i2c mode timing
12 ds578f3 cs8416 2. pin description - software mode 2.1 tssop pin description pin name pin # pin description va 6 analog power ( input ) - analog power supply. nominally +3.3 v. this supply should have as little noise as possible since noise on this pin will directly af fect the jitter performance of the recovered clock vd 23 digital power ( input ) ? digital core power supply. nominally +3.3 v vl 21 logic power ( input ) ? input/output power supply. nominally +3.3 v or +5.0 v agnd 7 analog ground ( input ) - ground for the analog circuitry in the chip. agnd and dgnd should be con- nected to a common ground area under the chip. dgnd 22 digital & i/o ground ( input ) - ground for the i/o and core logic. agnd and dgnd should be connected to a common ground area under the chip. rst 9 reset ( input ) - when rst is low, the cs8416 enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. filt 8 pll loop filter ( output ) - an rc network should be connected between this pin and analog ground. for minimum pll jitter, return the ground end of the filter network directly to agnd. see ?pll filter? on page 53 for more information on the pll and the external components. rxp0 rxp1 rxp2 rxp3 rxp4 rxp5 rxp6 rxp7 4 3 2 1 10 11 12 13 positive aes3/spdif input ( input ) - single-ended or diff erential receiver inputs carrying aes3 or s/pdif encoded digital data. the rxp[7:0] inputs compri se the 8:2 s/pdif input multiplexer. the select line control is accessed using the c ontrol 4 register (04h). unused mu ltiplexer inputs should be left float- ing or tied to agnd. see ?external aes3/spdif/i ec60958 receiver co mponents? on page 49 for rec- ommended input circuits. rxp3 olrck rxp2 osclk rxp1 sdout rxp0 omck rxn rmck va vd agnd dgnd filt vl rst gpo0 rxp4 gpo1 rxp5 ad2 / gpo2 rxp6 sda / cdout rxp7 scl / cclk ad0 / cs ad1 / cdin 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 top-down view 28-pin soic/tssop package
ds578f3 13 cs8416 rxn 5 negative aes3 /spdif input ( input ) - single-ended or di fferential receiver input carrying aes3 or s/pdif encoded digital data. used along with rxp[7:0] to form an aes3 differential input. in single- ended operation this should be ac coupled to ground through a capacitor. see ?external aes3/spdif/iec60958 receiver components? on page 49 for recommended input circuits. omck 25 system clock ( input ) - when the omck system clock mode is enabled using the swclk bit in the control 1 register, the clock signal input on this pin is automatically output thr ough rmck on pll unlock. omck serves as the reference signal for omck/rmck ratio expressed in register 18h. ?omck system clock mode? section on page 28 rmck 24 input section recovered master clock ( output ) - input section recovered master clock output from the pll. frequency defaults to 256x the sample rate (f s ) and may be set to 128x through the rmckf bit in the control 1 register (01h). rmck may also be se t to high impedance by the rxd bit in the control 4 register (04h). osclk 27 serial audio output bit clock ( input / output ) - serial bit clock for audio data on the sdout pin olrck 28 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs) sdout 26 serial audio output data ( output ) - audio data serial output pin. this pin must be pulled high to vl through a 47 k resistor to place the part in software mode. sda / cdout 17 serial control data i/o (i2c) / data out (spi) ( input/output ) - in i2c mode, sda is the control i/o data line. sda is open drain and requires an external pull-up resistor to vl. in spi mode, cdout is the out- put data from the control port interface on the cs8416. see the ?control port description? section on page 33 . scl / cclk 16 control port clock ( input ) - serial control interface clock and is used to clock control data bits into and out of the cs8416. cclk is an open drain output and r equires an external pull-up resistor to vl. see the ?control port description? section on page 33 . ad0 / cs 14 address bit 0 (i2c) / contro l port chip select (spi) ( input) - a falling edge on this pin puts the cs8416 into spi control port mode. with no falling edge, t he cs8416 defaults to i2c mode. in i2c mode, ad0 is a chip address pin. in spi mode, cs is used to enable the control port interface on the cs8416. see the ?control port description? section on page 33 . ad1 / cdin 15 address bit 1 (i2c) / serial control data in (spi) ( input ) - in i2c mode, ad1 is a chip address pin. in spi mode, cdin is the input data line for the control port interface. see the ?control port description? section on page 33 . ad2 / gpo2 18 general purpose output 2 (output) - if using the i2c control port, this pin must be pulled high or low through a 47 k resistor. see the ?control port description? section on page 33 and ?general purpose outputs? on page 29 for gpo functions. gpo1 19 general purpose output 1 (output) - see ?general purpose outputs? on page 29 for gpo functions. gpo0 20 general purpose output 0 (output) - see ?general purpose outputs? on page 29 for gpo functions. pin name pin # pin description
14 ds578f3 cs8416 2.2 qfn pin description pin name pin # pin description va 3 analog power ( input ) - analog power supply. nominally +3.3 v. this supply should have as little noise as possible since noise on this pin will directly af fect the jitter performance of the recovered clock vd 20 digital power ( input ) ? digital core power supply. nominally +3.3 v vl 18 logic power ( input ) ? input/output power supply. nominally +3.3 v or +5.0 v agnd 4 analog ground ( input ) - ground for the analog circuitry in the chip. agnd and dgnd should be con- nected to a common ground area under the chip. dgnd 19 digital & i/o ground ( input ) - ground for the i/o and core logic. agnd and dgnd should be connected to a common ground area under the chip. rst 6 reset ( input ) - when rst is low, the cs8416 enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. filt 5 pll loop filter ( output ) - an rc network should be connected between this pin and analog ground. for minimum pll jitter, return the ground end of the filter network directly to agnd. see ?pll filter? on page 53 for more information on the pll and the external components. 9 8 7 6 5 4 3 2 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 top-down view 28-pin qfn package thermal pad rxp1 rxp2 rxp3 olrck osclk sdout omck rxp5 rxp6 rxp7 ad0 / cs ad1 / cdin scl / cclk sda / cdout rxp0 rxn va agnd filt rst rxp4 rmck vd dgnd vl gpo0 gpo1 ad2 / gpo2
ds578f3 15 cs8416 rxp0 rxp1 rxp2 rxp3 rxp4 rxp5 rxp6 rxp7 1 28 27 26 7 8 9 10 positive aes3/spdif input ( input ) - single-ended or differential receiver inputs carrying aes3 or s/pdif encoded digital data. the rxp[ 7:0] inputs comprise the 8:2 s/pd if input multiplexer. the select line control is accessed using the co ntrol 4 register (04h). unused multip lexer inputs should be left float- ing or tied to agnd. see ?external aes3/spdif/iec60958 receiver components? on page 49 for rec- ommended input circuits. rxn 2 negative aes3 /spdif input ( input ) - single-ended or di fferential receiver input carrying aes3 or s/pdif encoded digital data. used along with rxp[7:0] to form an aes3 differential input. in single- ended operation this should be ac coupled to ground through a capacitor. see ?external aes3/spdif/iec60958 receiver components? on page 49 for recommended input circuits. omck 22 system clock ( input ) - when the omck system clock mode is enabled using the swclk bit in the control 1 register, the clock signal input on this pin is automatically output thr ough rmck on pll unlock. omck serves as the reference signal for omck/rmck ratio expressed in register 18h. ?omck system clock mode? section on page 28 rmck 21 input section recovered master clock ( output ) - input section recovered master clock output from the pll. frequency defaults to 256x the sample rate (f s ) and may be set to 128x through the rmckf bit in the control 1 register (01h). rmck may also be se t to high impedance by the rxd bit in the control 4 register (04h). osclk 24 serial audio output bit clock ( input / output ) - serial bit clock for audio data on the sdout pin olrck 25 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs) sdout 23 serial audio output data ( output ) - audio data serial output pin. this pin must be pulled high to vl through a 47 k resistor to place the part in software mode. sda / cdout 14 serial control data i/o (i2c) / data out (spi) ( input/output ) - in i2c mode, sda is the control i/o data line. sda is open drain and requires an external pull-up resistor to vl. in spi mode, cdout is the out- put data from the control port interface on the cs8416. see the ?control port description? section on page 33 . scl / cclk 13 control port clock ( input ) - serial control interface clock and is used to clock control data bits into and out of the cs8416. cclk is an open drain output and r equires an external pull-up resistor to vl. see the ?control port description? section on page 33 . ad0 / cs 11 address bit 0 (i2c) / contro l port chip select (spi) ( input) - a falling edge on this pin puts the cs8416 into spi control port mode. with no falling edge, t he cs8416 defaults to i2c mode. in i2c mode, ad0 is a chip address pin. in spi mode, cs is used to enable the control port interface on the cs8416. see the ?control port description? section on page 33 . ad1 / cdin 12 address bit 1 (i2c) / serial control data in (spi) ( input ) - in i2c mode, ad1 is a chip address pin. in spi mode, cdin is the input data line for the control port interface. see the ?control port description? section on page 33 . ad2 / gpo2 15 general purpose output 2 (output) - if using the i2c control port, this pin must be pulled high or low through a 47 k resistor. see the ?control port description? section on page 33 and ?general purpose outputs? on page 29 for gpo functions. gpo1 16 general purpose output 1 (output) - see ?general purpose outputs? on page 29 for gpo functions. gpo0 17 general purpose output 0 (output) - see ?general purpose outputs? on page 29 for gpo functions. thermal pad - thermal pad - thermal relief pad for optimized heat dissipation. pin name pin # pin description
16 ds578f3 cs8416 3. pin description - hardware mode 3.1 tssop pin description pin name pin # pin description va 6 analog power ( input ) - analog power supply. nominally +3.3 v. this supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock vd 23 digital power ( input ) ? digital core power supply. nominally +3.3 v vl 21 logic power ( input ) ? input/output power supply . nominally +3.3 v or +5.0 v agnd 7 analog ground ( input ) - ground for the analog circuitry in the chip. agnd and dgnd should be connected to a common ground area under the chip. dgnd 22 digital & i/o ground ( input ) - ground for the i/o and core logic. agnd and dgnd should be con- nected to a common ground area under the chip. rst 9 reset ( input ) - when rst is low, the cs8416 enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. filt 8 pll loop filter ( output ) - an rc network should be connected between this pin and analog ground. for minimum pll jitter, return the ground end of the filter network directly to agnd. see ?pll filter? on page 53 for more information on the pll and the external components. rxp0 rxp1 rxp2 rxp3 4 3 2 1 positive aes3/spdif input ( input ) - single-ended or differential re ceiver inputs carrying aes3 or s/pdif encoded digital data. the rxp[3:0] inputs comprise the 4:2 s/pdif input multiplexer. the select line control is accessed us ing the rxpsel[1:0] pins. unused multiplexer inpu ts should be left floating or tied to agnd. see ?external aes3/spdif/iec60958 re ceiver components? on page 49 for recommended input circuits. rxn 5 negative aes3 /spdif input ( input ) - single-ended or differential receiver input carrying aes3 or s/pdif encoded digital data. used along with rxp[3:0] to form an aes3 differential input. in single- ended operation this should be ac coupled to ground through a capacitor. see ?external aes3/spdif/iec60958 receiver components? on page 49 for recommended input circuits. rxp3 olrck rxp2 osclk rxp1 sdout rxp0 omck rxn rmck va vd agnd dgnd filt vl rst tx rxsel1 c rxsel0 u txsel1 rcbl txsel0 96khz nv / rerr audio 1 2 3 4 5 6 7 821 22 23 24 25 26 27 28 9 10 11 12 17 18 19 20 13 14 15 16 top-down view 28-pin soic/tssop package
ds578f3 17 cs8416 omck 25 system clock ( input ) - omck system clock mode is enabled by a transition (rising edge active) on omck after reset. when enabled, the clock signal input on this pin is automatically output through rmck on pll unlock. see ?omck system clock mode? on page 28 . rmck 24 input section recovered master clock ( output ) - input section recove red master clock output from the pll. frequency is 256x the sample rate (f s ) when the u pin is pulled down by a 47 k resistor to dgnd. frequency is 128x the sample rate (f s ) when the u pin is pulled up by a 47 k resistor to vl. osclk 27 serial audio output bit clock ( input / output ) - serial bit clock for audio data on the sdout pin olrck 28 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs) sdout 26 serial audio output data ( output ) - audio data serial output pin. this pin must be pulled low to dgnd through a 47 k resistor to place the part in hardware mode. rxsel1 rxsel0 10 11 receiver mux selector (input) - used to select which pin, rxp[3:0], is used for the receiver input. txsel1 txsel0 12 13 tx pin mux selection (input) - used to select which pin, rxp[3:0], is passed to the tx pin out- put. if tx passthrough is not used, the user should se t it to output one of the unused receiver inputs. tx 20 s/pdif mux passthrough ( output) - single-ended signal is resolved to full-rail, but is not de-jittered before it is output. output is set by txsel[1:0]. this pin is also used to select the type of phase detector (pdur) at reset. if tx passthrough is not used, the user should set it to output one of the unused receiver inputs. nv/rerr 14 non-validity receiver error/receiver error (output) - receiver error indicator. nverr is selected by a 47 k resistor to dgnd. rerr is selected by a 47 k resistor to vl. audio 15 audio channel status bit (output) ? when low, a valid linear pcm audio stream is indicated. see ?non-audio detection? on page 31 . this pin is also used to select the serial port format (sfsel1) at reset. 96khz 16 96 khz sample rate detect (output) - if the input sample rate is 48 khz, outputs a ?0?. outputs a ?1? if the sample rate is 88.1 khz. otherwise the output is in determinate. also used to set the emphasis audio match feature at reset. rcbl 17 receiver channel status block (output) -indicates the beginning of a received channel status block. rcbl goes high two frames after the reception of a z preamble, remains high for 16 frames and then returns low for the remainder of the block. rcbl changes on rising edges of rmck. also used to set the serial audio port to master or slave at reset. c19 channel status data ( output ) - outputs channel status data from the aes3 receiver, clocked by the rising and falling edges of olrck. also used to se lect the serial port format (sfsel0) at reset. u18 user data ( output ) - outputs user data from the aes3 receiver, clocked by the rising and falling edges of olrck. also used to select the frequency of rmck to either 256*f s or 128*f s at reset. pin name pin # pin description
18 ds578f3 cs8416 3.2 qfn pin description pin name pin # pin description va 3 analog power ( input ) - analog power supply. nominally +3.3 v. this supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock vd 20 digital power ( input ) ? digital core power supply. nominally +3.3 v vl 18 logic power ( input ) ? input/output power supply . nominally +3.3 v or +5.0 v agnd 4 analog ground ( input ) - ground for the analog circuitry in the chip. agnd and dgnd should be connected to a common ground area under the chip. dgnd 19 digital & i/o ground ( input ) - ground for the i/o and core logic. agnd and dgnd should be con- nected to a common ground area under the chip. rst 6 reset ( input ) - when rst is low, the cs8416 enters a low power mode and all internal states are reset. on initial power up, rst must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. filt 5 pll loop filter ( output ) - an rc network should be connected between this pin and analog ground. for minimum pll jitter, return the ground end of the filter network directly to agnd. see ?pll filter? on page 53 for more information on the pll and the external components. rxp0 rxp1 rxp2 rxp3 1 28 27 26 positive aes3/spdif input ( input ) - single-ended or differential re ceiver inputs carrying aes3 or s/pdif encoded digital data. the rxp[3:0] inputs comprise the 4:2 s/pdif input multiplexer. the select line control is accessed us ing the rxpsel[1:0] pins. unused multiplexer inpu ts should be left floating or tied to agnd. see ?external aes3/spdif/iec60958 re ceiver components? on page 49 for recommended input circuits. 9 8 7 6 5 4 3 2 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 top-down view 28-pin qfn package thermal pad rxp1 rxp2 rxp3 olrck osclk sdout omck rxsel0 txsel1 txsel0 nv / rerr audio 96khz rcbl rxp0 rxn va agnd filt rst rxsel1 rmck vd dgnd vl tx c u
ds578f3 19 cs8416 rxn 2 negative aes3/spdif input ( input ) - single-ended or differential receiver input carrying aes3 or s/pdif encoded digital data. used along with rxp[3: 0] to form an aes3 differential input. in single- ended operation this should be ac coupled to ground through a capacitor. see ?external aes3/spdif/iec60958 receiver components? on page 49 for recommended input circuits. omck 22 system clock ( input ) - omck system clock mode is enabled by a transition (rising edge active) on omck after reset. when enabled, the clock signal input on this pin is automatically output through rmck on pll unlock. see ?omck system clock mode? on page 28 . rmck 21 input section recovered master clock ( output ) - input section recove red master clock output from the pll. frequency is 256x the sample rate (f s ) when the u pin is pulled down by a 47 k resistor to dgnd. frequency is 128x the sample rate (f s ) when the u pin is pulled up by a 47 k resistor to vl. osclk 24 serial audio output bit clock ( input / output ) - serial bit clock for audio data on the sdout pin olrck 25 serial audio output left/right clock ( input / output ) - word rate clock for the audio data on the sdout pin. frequency will be the output sample rate (fs) sdout 23 serial audio output data ( output ) - audio data serial output pin. this pin must be pulled low to dgnd through a 47 k resistor to place the part in hardware mode. rxsel1 rxsel0 7 8 receiver mux selector (input) - used to select which pin, rxp[3:0], is used for the receiver input. txsel1 txsel0 9 10 tx pin mux selection (input) - used to select which pin, rxp[3:0], is passed to the tx pin out- put. if tx passthrough is not used, the user should se t it to output one of the unused receiver inputs. tx 17 s/pdif mux passthrough ( output) - single-ended signal is resolved to full-rail, but is not de-jittered before it is output. output is set by txsel[1:0]. this pin is also used to select the type of phase detector (pdur) at reset. if tx passthrough is not used, the user should set it to output one of the unused receiver inputs. nv/rerr 11 non-validity receiver error/receiver error (output) - receiver error indicator. nverr is selected by a 47 k resistor to dgnd. rerr is selected by a 47 k resistor to vl. audio 12 audio channel status bit (output) ? when low, a valid linear pcm audio stream is indicated. see ?non-audio detection? on page 31 . this pin is also used to select the serial port format (sfsel1) at reset. 96khz 13 96 khz sample rate detect (output) - if the input sample rate is 48 khz, outputs a ?0?. outputs a ?1? if the sample rate is 88.1 khz. otherwise the output is in determinate. also used to set the emphasis audio match feature at reset. rcbl 14 receiver channel status block (output) -indicates the beginning of a received channel status block. rcbl goes high two frames after the reception of a z preamble, remains high for 16 frames and then returns low for the remainder of the block. rcbl changes on rising edges of rmck. also used to set the serial audio port to master or slave at reset. c16 channel status data ( output ) - outputs channel status data from the aes3 receiver, clocked by the rising and falling edges of olrck. also used to se lect the serial port format (sfsel0) at reset. u15 user data ( output ) - outputs user data from the aes3 receiver, clocked by the rising and falling edges of olrck. also used to select the frequency of rmck to either 256*f s or 128*f s at reset. thermal pad - thermal pad - thermal relief pad for optimized heat dissipation. pin name pin # pin description
20 ds578f3 cs8416 4. typical connection diagrams figure 5. typical connection diagram - software mode * a separate analog supply is only necessary in applicatio ns where rmck is used for a jitter sensitive task. for applications where rmck is not used for a jitter sensitive task, connect va to vd via a ferrite bead. keep decou- pling capacitors between va and agnd. ** see ?s/pdif receiver? on page 27 and ?external aes3/spdif/iec60958 receiver components? on page 49 for typical input configurations and recommended input circuits. *** for best jitter performance, connect the filt er ground directly to the agnd pin. see table 6 on page 54 for pll filter values. cs8416 filt dgnd agnd ** *** rxn rxp0 rxp1 rxp2 rxp3 aes3 / s/pdif sources microcontroller scl / cclk sda / cdout omck clock source rst ad1 / cdin gpo0 rmck clock control serial audio input device olrck osclk sdout external interface rxp4 rxp5 rxp6 rxp7 ad0 / cs gpo1 ad2/gpo2 r flt c flt c rip 47k 10 f +3.3 v or +5 v 0.1 f +3.3 v ferrite bead +3.3 v analog supply * va vd vl * 0.1 f 0.1 f vl vl
ds578f3 21 cs8416 figure 6. typical connection diagram - hardware mode * these pins must be pulled high to vl or low to dgnd through a 47 k resistor. ** a separate analog supply is only necessary in applicatio ns where rmck is used for a jitter sensitive task. for applications where rmck is not used for a jitter sensitive task, connect va to vd via a ferrite bead. keep decou- pling capacitors between va and agnd. *** see ?s/pdif receiver? on page 27 and ?external aes3/spdif/iec60958 re ceiver components? on page 49 for typical input configurations and recommended input circuits. **** for best jitter performance connect the f ilter ground directly to the agnd pin. see table 6 on page 54 for pll filter values. 10 f cs8416 0.1 f +3.3 v filt dgnd agnd r flt c flt c rip *** **** rxn rxp0 rxp1 rxp2 rxp3 aes3 / s/pdif sources hardware control rxsel1 txsel0 txsel1 nv/rerr 96khz rcbl u c ferrite bead +3.3 v analog supply ** omck clock source rxsel0 rst audio va vd vl tx rmck clock control serial audio input device olrck osclk sdout external interface 47k ** * * * * * * 0.1 f 0.1 f +3.3 v or +5 v vl vl *
22 ds578f3 cs8416 5. applications 5.1 reset, power-down and start-up when rst is low, the cs8416 enters a low power mode and all internal states are reset, including the con- trol port and registers, and the output s are muted. in software mode, when rst is high, the control port becomes operational, and the desired settings should be lo aded into the control registers. writing a 1 to the run bit will then cause the part to leave the low powe r state and begin o peration. after the pll has settled, the serial audio out puts will be enabled. some options within the cs8416 are controlled by a st art-up mechanism. during the reset state, some of the pins are reconfigured internally to be inputs. immediately upon exiting the reset state, the level of these pins is sensed. the pins are then switched to be outputs. this mechanism allows output pins to be used to set alternative modes in the cs8416 by connecting a 47 k resistor to between the pin and either vl (hi) or dgnd (lo). for each mode, every start-up option se lect pin must have an ex ternal pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup conditions (except for tx, which has an internal pull-down). in software mode, t he only start-up option pins are gpo2, which are used to set a chip address bit for the control port in i2c mode, and sdout, which selects between hardware and software modes. the hardware mode uses ma ny start-up options, which are detailed in section 15.2 ?hard- ware mode function selection? on page 46 . 5.2 id code and revision code the cs8416 has a register that contains a 4-bit code to indicate that the addressed device is a cs8416. this is useful when other cs84xx family members are resident in the same system, allowing common soft- ware modules. the cs8416 4-bit revision code is also available. this allows the software driver for the cs8416 to identify which revision of the device is in a particular system , and modify its behavior accordingly. to allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcon- troller, and used wherever appropriate as revision details become known. 5.3 power supply, gr ounding, and pcb layout for most applications, the cs8416 can be operated fr om a single +3.3 v supply, following normal supply decoupling practices (see figures 5 and 6 ). for applications where the recovered input clock, output on the rmck pin, is required to be low jitter, then use a se parate, quiet, analog +3.3 v supply for va, decoupled to agnd. make certain that no digital traces are rout ed near va, agnd, or filt as noise may couple and degrade performance. these pins should be well isol ated from switching signals and other noise sources. vl sets the level for the digital inputs and ou tputs, as well as the aes/spdif receiver inputs. extensive use of powe r and ground planes, ground plane fill in unused areas and surfac e mount decoupling capacitors are recommended. decoupling capacitors sh ould be mounted on the same side of the board as the cs8416 to minimize inductance effects, and all de coupling capacitors should be as close to the cs8416 as possible. see ?pll filter? on page 53 for layout recommendations for the pll.
ds578f3 23 cs8416 6. general description the cs8416 is a monolithic cmos device that receives and decodes audio data acco rding to the aes3, iec60958, s/pdif, and eiaj cp1201 interface standards. the cs8416 provides an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the cs8416. input data can be ei ther differential or single-ended. a low jitter clock is re- covered from the incoming data using a pll. the decoded audio data is output through a configurable, 3-wire serial audio output port. the channel status and q-channel subc ode portion of the user data are assembled in registers and may be accessed through an spi or i2c port. three general purpose output (gpo) pins are provided to allow a variety of signals to be accessed under software control. in hardware mode, dedicated pins are used to se lect audio stream inputs for decoding and transmission to a dedicated tx pin. hardware mode also provi des channel status and user data output pins. figures 5 and 6 show the power supply and external connections to the cs8416 when configured for software mode and hardware mode. please note that all i/o pins, including rxn and rxp[7:0], operate at the vl voltage. 6.1 aes3 and s/pdif standards documents this document assumes that the user is familiar with the aes 3 and s/pdif data format s. it is advisable to have current copies of the aes3, iec60958, and iec6 1937 specifications on hand for easy reference. the latest aes3 standard is available from the audio engi neering society or ansi at www.aes.org or at www.ansi.org . obtain a copy of the latest iec60958/61937 st andard from ansi or from the international electrotechnical commission at www.iec.ch . the latest eiaj cp-1201 standard is available from the japanese electronics bureau. application note 22: overview of digital audio interface data structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. the paper an understanding and implemen tation of the scms serial c opy management system for digital audio transmission , by clifton sanchez, is an excellent tuto rial on scms. it is available from the aes as reprint 3518. 7. serial audio output port a 3-wire serial audio output port is provided. the port ca n be adjusted to suit the attac hed device by setting the con- trol registers. the following parameters are adjustable: mast er or slave, serial clock frequency, audio data resolu- tion, left- or right-justification of the data relative to lef t/right clock, optional one-bit cell delay of the first data bit, the polarity of the bit clock, and the polarity of the left/right clock. by setting the appropriate control bits, many formats are possible. figure 7 shows a selection of common output formats, along with the control bit settings. a special aes3 direct out- put format is included, which allows the serial output port access to the v, u, and c bits embedded in the serial audio data stream. when using the part in aes3 direct-output format, the de-emphasis filter must be off (see section 14.4 on page 38 ). the p bit, which would normally be a parity bit, is repl aced by a z bit, which is used to indicate the start of each block. the received channel st atus block start signal is also available as the rcbl pin in hardware mode and through a gpo pin in software mode. in master mode, the left/right clock (olrck) and the serial bit clock (osclk ) are outputs, derived from the recov- ered rmck clock. in slave mode, olrck and osclk are in puts. olrck is normally synchronous to the appropri- ate master clock, but osclk can be asynchronous and disc ontinuous if required. by ap propriate phasing of olrck and control of the serial clocks, mult iple cs8416?s can share one serial port. olrck should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to
24 ds578f3 cs8416 clock all the data bits. when in slave mode, the serial audio output port cannot be set for right-justified data. the cs8416 allows immediate mute of the serial audio output po rt audio data by the mutesao bit of control register 1. for more information about serial audio formats, refer to the cirrus logic applications note an282, ?the 2-channel serial audio interface: a tutorial?, available at www.cirrus.com . figure 7. serial audio output example formats x = don?t care to match format, but does need to be set to the desired setting * see serial output data format register bit descriptions for an explanation of the meaning of each bit soms* sosf* sores[1:0]* soj ust* sodel* sospol* solrpol* left-justified x x xx 0 0 0 0 i2s x x xx 0 1 0 1 right-justified 1 x xx 1 0 0 0 aes3 direct x x 11 0 0 0 0 olrck osclk sdout channel a channel b left justified (out) olrck osclk channel a sdout channel b i2s (out) olrck osclk channel a channel b msb sdout msb lsb lsb msb extended msb extended right justified (out) olrck osclk channel a channel b msb sdout lsb lsb channel a channel b lsb lsb msb msb msb aes3 direct (out) msb msb msb lsb lsb msb lsb msb lsb msb c u v z c u v c u v c u v frame 191 frame 0 z
ds578f3 25 cs8416 7.1 slip/repeat behavior when using the serial audio output port in slave mode with an olrck input that is asynchronous to the incoming aes3 data, the interr upt bit oslip (bit 5 in the interrupt 1 st atus register, 0dh) is provided to in- dicate when repeated or dropped samples occur. refer to figure 8 for the aes3 data format diagram. when the serial output port is conf igured as slave, depending on the relative frequency of olrck to the input aes3 data (z/x) preambl e frequency, the data will be slipped or repeated at the output of the cs8416. after a fixed delay from the z/x preamble (a few periods of the internal clock, which is running at 256fs), the circuit will look back in time until the previous z/ x preamble and check which of the followi ng conditions occurred: 1. if during that time, the internal data buffer was not updated, a slip has occurred. data from the previous frame will be output and oslip will be set to 1. due to the oslip bit being ?sticky,? it will remain 1 until the register is read. it w ill then be reset unt il another slip/repea t condition occurs. 2. if during that time the internal data buffer did not update between two positive or negative edges (de- pending on olrpol) of olrck, a repeat has occurred. in this case, the buffer data was updated twice, so the part has lost one frame of data . this event will also trigger oslip to be set to 1. due to the oslip bit being ?sticky,? it will remain 1 until the register is read. it will then be reset until another slip/repeat condition occurs. 3. if during that time, it did see a positive edge on olrck (or negative edge if the solrpol is set to 1) no slip or repeat ha s happened. due to the oslip bit being ?sticky,? it will remain in its previous state until either the register is read or a slip/repeat condition occurs. if the user reads oslip as soon as the event triggers, over a long pe riod of time the rate of occurring int will be equal to the differ ence in freq uency between the input aes data and the sl ave serial output lrck. the cs8416 uses a hysteresis window when a slip/repe at event occurs. the slip/repeat is triggered when an edge of olrck passes a window size from the beginning of the z/x preamble. without the hysteresis window, jitter on olrck with a frequency very close to fs could slip back and forth, causing multiple slip/re- peat events. the cs8416 uses a hysteresis window to ensure that only one slip/repeat happens even with jitter on olrck figure 8. aes3 data format x channel a data y channel b data z y x y channel a data channel b data channel a data channel b data frame 191 frame 0 frame 1 preambles olrck (in slave mode)
26 ds578f3 cs8416 7.2 aes11 behavior when olrck is configured as a master, the positive or negative edge of olrck (depending on the setting of solrpol in register 05h) will be wi thin -1.0%(1/fs) to 1.1% (1/fs) from the start of the preamble x/z. in master mode, the latency through the part is dependent on the input sample frequency. the typical delay through the part from the beginning of the preamble to the active edge of olrck for the various sample frequencies is given in table 1 . in master mode without the de-emphasis filter engaged, the latency of the audio data will be 3 frames. when olrck is configured as a slave, any synchronize d input within +/-28%(1/fs) from the positive or neg- ative edge of olrck (depending on the setting of solrpol in register 05h) will be treated as being sam- pled at the same time. since the cs8416 has no contro l of the olrck in slave mode, the latency of the data through the par t will be a multiple of 1/fs plus th e delay between olrck and the preambles. both of these conditions are within the to lerance range set fort h in the aes11 standard. fs (khz) delay (ns) 32 98.0 44.1 80.5 48 78.0 64 67.0 96 57.5 192 47.0 table 1. typical delays by frequency values
ds578f3 27 cs8416 8. s/pdif receiver the cs8416 includes an aes3/spdif digital audio receiver. the receiver accepts and decodes bi-phase encoded audio and digital data according to the aes3, iec60958 (s/pdif) , and eiaj cp-1201 inte rface standards. the re- ceiver consists of an analog differenti al input stage, driven through analog input pins rxp0 to rxp7 and a common rxn, a pll based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. external components are used to terminat e the incoming data cables and isolate the cs8416. these components are detailed in ?external aes3/spdif/iec60958 rece iver components? on page 49 . figure 9 shows the input structure of the receiver. 8.1 8:2 s/pdif i nput multiplexer 8.1.1 general the cs8416 employs a 8:2 s/pdif input multiplexer to accommodate up to eight channels of input digital audio data. digital audio data may be single-ended or differ ential. differential inpu ts utilize rxp[7:0] and a shared rxn. single ended signals are accommodate d by using the rxp[7:0] inputs and ac coupling rxn to ground. all active inputs to the cs8416 8:2 input multiplexer should be coupled through a capacitor as these inputs are biased at vl/2 when selected. these inputs are floating when not selected. unused multiplexer inputs should be left floating or tied to agnd. the recommended capacitor value is 0.01 f to 0.1 f. the rec- ommended dielectrics for the ac coupling capacitors are c0g or x7r. the input voltage range for the input multiplexer is se t by the i/o power supply pin, vl. the input voltage of the rxp[7:0] and rxn pins is also set by the leve l of vl. input signals with voltage levels above vl or below dgnd may degrade performance or damage the part. 8.1.2 software mode the multiplexer select line control is accessed through bits rxsel[2:0] in control port register 04h. the multiplexer defaults to rxp0. + - vl 22 k (22000/n) 22 k vl = 5.0 v: 2.3 k vl = 3.3 v: 3.0 k agnd rxn rxp[7:0] vl = 5.0 v: (1500 + 800/n) vl = 3.3 v: (1500 + 1500/n) (22000/n) figure 9. receiv er input structure if rxp[7:0] is selected by either the r eceiver mux or the tx passthrough mux, n=1. if rxp[7:0] is selected by both the receiver mux and the tx passthrough mux, n=2. if rxp[7:0] is not selected at all, n=0 (i.e. high impedance).
28 ds578f3 cs8416 the second output of the input multiplexer is used to provide the selected input as a source to be output on a gpo pin. this pass through signal is selected by txsel[2:0] in control port register 04h. this single- ended signal is resolved to full-rail, but is not de-jittered before it is output. 8.1.3 hardware mode in hardware mode the input to the decoder is selected by dedicated pins, rxsel[1:0]. the pass through signal is selected by dedicated pins, txsel[1:0] for output on the dedicated tx pin. this single-ended signal is resolved to full-ra il, but is not de-jittered before it is output. selectable inputs are restricted to rxp0 to rxp3 for both the receiver and the tx output pin. these inputs are selected by rxsel[1:0] and txsel[1:0] respectively. 8.2 omck system clock mode a special clock switching mode is available that allows the omck clock input to automatically replace rmck when the pll becomes unlocked. this is accomp lished without spurious transitions or glitches on rmck. in hardware mode this feature is enabled by a transition (rising edge active) on the omck pin after reset. therefore to not enable the clock switching feature in hardware mode, omck should be tied to dgnd or vl. however, in hardwa re mode, once the clock switching feature has been enabled, it can only be dis- abled by resetting the part. in software mode the automatic clock switching feature is enabled by setting swclk bit in control1 register to a ?1?. additiona lly in software mode, omck can be manually forced to output on rmck by using the fswclk bit in the control0 register. when the clock switching feature is enabled, osclk and olrck are derived from the omck input when the clock has been switched and the serial port is in master mode. when clock switching is enabled and the pll is not locked, olrck will be omck/256 and osclk will be omck/4 . when the pll loses lock, the frequency of the vco drops to ~750 khz. when this system clock mode is not enabled, the osclk and olrck will be based on the vco when the pll is not locked and has reac hed its steady-state idle frequen- cy. table 2 shows an example of output clocks based on clock switching being enabled or disabled. 8.3 clock recover y and pll filter please see ?pll filter? on page 53 for a general description of the pl l, selection of recommended pll filter components, and layout considerations. figures 5 and 6 show the recommended co nfiguration of the two capacitors and one resistor that comprise the pll filter. clock switching enabled/disabled pll locked/unlocked rmck clock ratio rmck osclk olrck disabled locked 128*f s 6.144 mhz 3.072 mhz 48 khz enabled locked 128*f s 6.144 mhz 3.072 mhz 48 khz disabled unlocked 128*f s ~375 khz ~187.5 khz ~2.925 khz enabled unlocked 128*f s 11.2896 mhz 2.8224 mhz 44.1 khz disabled locked 256*f s 12.288 mhz 3.072 mhz 48 khz enabled locked 256*f s 12.288 mhz 3.072 mhz 48 khz disabled unlocked 256*f s ~750 khz ~187.5 khz ~2.925 khz enabled unlocked 256*f s 11.2896 mhz 2.8224 mhz 44.1 khz example with omck = 11.2896 mhz, the receiver input sample rate = 48 khz, oslck = 64*fs, and fswclk (software mode only) = ?0?. table 2. clock switching output clock rates
ds578f3 29 cs8416 9. general purp ose outputs three general purpose outputs (gpo) ar e provided to allow the equipment designer flexib ility in configuring the cs8416. fourteen signals are available to be routed to an y of the gpo pins. the outputs of the gpo pins are set through the gpoxsel[3:0] bits in the control2 (02h) and co ntrol3 (03h) registers. all gpo pins default to gnd after reset. gpo pins may be configured to provide the following data: notes: 1. frequency = 25 mhz max, duty cycle not guaranteed, target duty cycle = 50% @ f s = 48 khz. function code definition gnd 0000 fixed low level emph 0001 state of emph bit in the incoming data stream. int 0010 cs8416 interrupt output c 0011 channel status bit u 0100 user data bit rerr 0101 receiver error nverr 0110 non-validity receiver error rcbl 0111 receiver channel status block 96khz 1000 if the input sample rate is 48 khz, outputs a ?0?. outputs a ?1? if the sample rate is 88.1 khz. otherwise the output is indeterminate. audio 1001 non-audio indicator for decoded input stream vlrck 1010 virtual lrck. can be used to frame the c and u output data. tx 1011 pass through of aes/spdif input selected by txsel[2:0] in the control 4 register (04h) vdd 1100 vdd fixed high level hrmck 1101 f s x 512 (note 1) codes 1110 to 1111 - reserved table 3. gpo pin configurations
30 ds578f3 cs8416 10.error and status reporting 10.1 general while decoding the incoming bi-phase encoded data str eam, the cs8416 has the ab ility to identify various error conditions. 10.1.1 software mode software mode allows the most flex ibility in reading errors. when unma sked, bits in the receiver error register (0ch) indicate the following errors: 1. qcrc ? crc error in q subcode data. 2. ccrc ? crc error in channel status data. 3. unlock ? pll is not locked to incoming data stream. 4. v ? data validity bit is set. 5. conf ? the logical or of unlock and bip. the input data stream may be near error condition due to jitter degradation. 6. bip ? biphase encoding error. 7. par ? parity error in incoming data. the error bits are ?sticky,? meaning that they are set on the first occu rrence of the associated error and will remain set until th e user reads the regist er through the c ontrol port. this enables the register to log all unmasked errors that occurred since the last time the register was read. as a result of the bits ?stickiness,? it is necessary to perform two reads on these registers to see if the error condition still exists. the receiver error mask register (06h) allows masking of individual errors. the bits in this register default to 00h and serve as masks for the corresponding bits of the receiver error register. if a mask bit is set to 1, the error is unmasked, wh ich implies the following: it s occurrence will be report ed in the receiver error register, induce a pulse on rerr, in voke the occurrence of a rerr interrupt, and affect the current audio sample according to the status of the hold bits . the exceptions are the qcrc and ccrc errors, which do not affect the current audio sample, even if unmasked. the hold bits allow a choice of: ? holding the previous sample ? replacing the current sample with zero (mute) or ? not changing the current audio sample 10.1.2 hardware mode in hardware mode, the user may only choose betw een non-validity receiver error (nverr) or receiver error (rerr) by pulling the nv/rerr pin low or high, respectively. t he pull-up/pu ll-down condition will be sensed on start-up , and the approp riate error reporting will be set. rerr ? the previous audio sample is held and passed to the serial audio output port if the validity bit is high, or a parity, bi-phase, confidence or pll lock error occurs during the current sample. nverr ? the previous audio sample is held and passed to the serial audio output port if a parity, bi- phase, confidence or pll lock erro r occurs during the current sample.
ds578f3 31 cs8416 10.2 non-audio detection an aes3 data stream may be used to convey non-audio data, thus it is important to know whether the in- coming aes3 data stream is digital audio or not. this in formation is typically convey ed in channel status bit 1, which is extracted automatically by the cs8416. ho wever, certain non-audio sources, such as ac-3? or mpeg encoders, may not adhere to th is convention, and the bit may no t be properly set. the cs8416 aes3 receiver can detect such non-audio data through the use of an autodetect module. the autodetect module is similar to autodetect softwar e used in cirrus logic dsps. if the aes3 stream contains sync codes in the proper format for iec61937 or dts ? data transmission, an internal autodetect signal will be asserted. if th e sync codes no longer ap pear after a certain amount of time, autodetection will time-out and autodetect will be de-asserted until another format is detected. the audio signal is the logical or of autodetect an d the received channel status bit 1 (as decoded according to the chs bit in the control1 register). in hardware mode, audio is output on pin 15. in software mode, audio is available through the gpo pins. if non-audio data is detected, the data is still proces sed exactly as if it were no rmal audio. the exception is the use of de-emphasis auto-select feature which will bypass the de-emphasis filter if the input stream is detected to be non-audio. it is up to the user to mute the outputs as required. 10.2.1 format detection in software mode, the cs8416 can automatically dete ct various serial audio input formats. the format detect status regi ster (0bh) is used to indica te a detected format . the register will indicate if uncom- pressed pcm data, iec61937 data, dts_ld data, dts_ cd data, or digital silence was detected. addi- tionally, the iec61937 pc/pd burst preambles are av ailable in registers 23h-26h. see the register descriptions for more information. 10.3 interrupts the cs8416 has a comprehe nsive interrupt capability. the int sig nal, available in software mode, indi- cates when an interrupt condition has occurred and may be output on one of the gpos. it can also be set through bits int[1:0] in the control1 register (01h) to be active low, acti ve high or active low with no active pull-up transistor. this last mode is used for active low, wired-or hook- ups, with multiple peripherals con- nected to the microcontroller interrupt input pin. many conditions can cause an interrupt, as listed in th e interrupt status register descriptions. each source may be masked off thro ugh mask register bi ts. in addition, each source ma y be set to risi ng edge, falling edge, or level sensitive. combined with the option of le vel sensitive or edge sens itive modes within the mi- crocontroller, many different config urations are possible, depending on the needs of the equipment design- er. refer to the register descriptions for the interr upt mask (07h), interrupt mo de msb (08h), interrupt mode lsb (09h), and interrupt 1 status (0dh) registers
32 ds578f3 cs8416 11.channel status an d user-data handling ?channel status buffer management? on page 51 describes channel status and user data control. 11.1 software mode in software mode, several options are available for acce ssing the channel status and user data that is en- coded in the received aes3/spdif stream. the first option allows access directly through regist ers. the first 5 bytes of the channel status block are decoded into the receiver channel status registers 19h - 22h. registers 19h - 1dh contain the a channel status data. registers 1eh - 22h contain the b channel status data. received channel status (c), user (u), and emph bits may also be output to the gpo pins by appropriately setting the gpoxsel bits in control port registers 02h and 03h. in serial port master mode, olrck and rcbl can be made available to qualify the u data output. in serial port slave mode, vlrck and rcbl can be made available to qualify the u data output. vlrck is a virtual word clock, equal to the receiver recov- ered sample rate, that can be used to frame the c/ u output. vlrck and rcbl are available through the gpo pins. figure 10 illustrates timing of the c and u data and their related signals. the user may also access all of the c and u bits dire ctly from the output data stream (sdout) by setting bits sores[1:0]=11 (aes3 direct mo de) in the serial audio data form at register (05h) . the appropriate bits can be stripped from the sdout signal by external control logic such as a dsp or microcontroller. if the incoming user data bits have been encoded as q-channel subcode, the data is decoded, buffered, and presented in 10 consecut ive register locations (0eh-17h). an interrupt may be enabled to indicate the decoding of a new q-channel block, whic h may be read through the control port. the encoded channel st atus bits which indicate sample word length are decoded according to aes3-1992 or iec 60958. the number of auxiliary bi ts are reported in bits 7 to 4 of the receiver channe l status register (0ah). 11.2 hardware mode in hardware mode, received channel status (c), and us er (u) bits are output on pins 19 and 18. in serial port master mode, olrck and rcbl are made av ailable to qualify the c and u data output. figure 10 il- lustrates timing of the c and u data and their related signals. the user may also access a ll of the c and u bits directly from the output data stream (sdout) by pulling the audio and c pins high through 47 k resistors to vl (aes3 direct mo de). the appropriate bits can be stripped from the sdout signal by external control logic such as a dsp or microcontroller. only olrck in master mode is available to qualify the u output. see ?hardware mode function selection? on page 46 and ?hardware mode equivalent register settings? on page 47 to configure these pins.. figure 10. c/u data outputs ? rcbl goes high 2 frames after receipt of a z preamble and is high for 16 frames. ? vlrck is a virtual work clock, available through the gpo pins, that can be used to frame the c/u output. ? vlrck duty cycle is 50%. vlrck freq uency is always equal to the incoming rcbl (out) vlrck (out) c/u (out)
ds578f3 33 cs8416 12.control port description the control port is used to access the registers, allowi ng the cs8416 to be configured for the desired operational modes and formats. the operation of the control port ma y be completely asynchronous with respect to the audio sample rates. however, to avoid potential interference pr oblems, the control port pins should remain static if no op- eration is required. the control port has 2 modes: spi and i2c, with the cs84 16 acting as a slave device. spi mode is selected if there is a high to low transition on the ad0/cs pin, after the rst pin has been brought high. i2c mode is selected by con- necting the ad0/cs pin through a resistor to vl or dgnd, ther eby permanently selecting the desired ad0 bit ad- dress state. 12.1 spi mode in spi mode, cs is the cs8416 chip select signal, cclk is the control port bit clock (input into the cs8416 from the microcontroller), cdin is the input data line from the microcontr oller, cdout is the output data line to the microcontroller. data is clocked in on the rising edge of cclk and out on the falling edge. figure 11 shows the operation of the co ntrol port in spi mode. to write to a register, bring cs low. the first seven bits on cdin form the chip address and must be 0010000. the eighth bit is a read/write indicator (r/w ), which should be low to write. the next eight bi ts include the 7-bit memory address pointer (map), which is set to the address of the r egister that is to be updated. the ne xt eight bits are the data which will be placed into the register designated by the map. du ring writes, the cdout output stays in the hi-z state. it may be externally pulled high or low with a 47 k resistor, if desired. to read a register, the map has to be set to the corr ect address by executing a partial write cycle which finishes (cs high) immediately after the map byte. to begin a read, bring cs low, send out the chip address and set the read/write bit (r/w ) high. the next falling edge of cclk will clock out the ms b of the addressed register (cdout will leave the high impedance state). the map automatically increm ents, so data for suc- cessive registers will appear consecutively. map msb lsb data byte 1 byte n r/w r/w address chip address chip cdin cclk cs cdout msb lsb msb lsb 0010000 0010000 map = memory address pointer, 8 bits, msb first high impedance figure 11. control port timing in spi mode
34 ds578f3 cs8416 12.2 i2c mode in i2c mode, sda is a bidirectional data line. data is cl ocked into and out of the part by the clock, scl. there is no cs pin. pins ad0 and ad1 form the two least significant bits of the chip address and should be con- nected through a resistor to vl or dgnd as desired. the gpo2 pin is used to set the ad2 bit by connecting a 47 k resistor from the gpo2 pin to vl or to dgnd. the states of the pins are sensed while the cs8416 is being reset. the signal timings for a read and write cycle are shown in figures 12 and 13 . a start condition is defined as a falling transition of sda while th e clock is high. a stop condition is a rising transition while the clock is high. all other transitions of sda occur while the clock is low. the first byte sent to the cs8416 after a start condition consists of a 7-bit chip address field and a r/w bit (high for a read, low for a write). the upper 4 bits of the 7-bit address field are fixed at 0010. to co mmunicate with a cs8416, the chip address field, which is the first byte sent to the cs8416, should match 0010 followed by the settings of the ad2, ad1, and ad0 pins. the eighth bit of the address is the r/w bit. if the operation is a write, the next byte includes the mem- ory address pointer (map) which selects the register to be read or writte n. if the operation is a read, the contents of the re gister pointed to by the map will be output. the m ap automatically in crements, so data from successive regist ers will appear consec utively. each byte is separated by an acknowledge bit (ack). the ack bit is output from the cs8416 after each input byte is read, and is input to the cs8416 from the microcontroller after each transmitted byte. note that the read operation can not set the map, so an aborted write operation is used as a preamble. as shown in figure 13 , the write operation is aborted after the ac knowledge for the map byte by sending a stop condition. 4 5 6 7 24 25 scl chip address (write) map byte data data +1 start ack stop ack ack ack 0 0 1 0 ad2 ad1 ad0 0 sda 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0 0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28 26 data +n 0 figure 12. control port timing, i2c slave mode write scl chip address (write) map byte data data +1 start ack stop ack ack ack sda chip address (read) start 6 5 4 3 2 1 0 7 0 7 0 7 0 no 16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28 2 3 10 11 17 18 19 25 ack data + n stop 0 0 1 0 ad2 ad1 ad0 0 0 0 1 0 ad2 ad1 ad0 1 0 figure 13. control port timing, i2c slave mode read
ds578f3 35 cs8416 13.control port regi ster quick reference addr (hex) r/wfunction76543210 00 r/w control0 0 fswclk 0 0 pdur trunc reserved reserved 01 r/w control1 swclk mutsao int1 int0 hold1 hold0 rmckf chs 02 r/w control2 detci emph_cn tl2 emph_cn tl1 emph_cn tl0 gpo0sel3 gpo0sel2 gpo0sel1 gpo0sel0 03 r/w control3 gpo1sel3 gpo1sel2 gpo1sel1 gpo 1sel0 gpo2sel3 gpo2sel2 gpo2sel1 gpo2sel0 04 r/w control4 run rxd rxsel2 rxsel1 rxsel0 txsel2 txsel1 txsel0 05 r/w serial audio data format soms sosf sores1 sores0 sojust sodel sospol solrpol 06 r/w receiver error mask 0 qcrcm ccrcm unlockm vm confm bipm parm 07 r/w interrupt mask 0 pcchm oslipm detcm cchm rerrm qchm fchm 08 r/w interrupt mode msb 0 pcch1 oslip1 detc1 cch1 rerr1 qch1 fch1 09 r/w interrupt mode lsb 0 pcch0 oslip0 detc0 cch0 rerr0 qch0 fch0 0a r receiver channel status aux3 aux2 aux1 aux0 pro copy orig emph 0b r audio format detect 0 pcm iec61937 dts_ld dts_cd reserved dgtl_sil 96khz 0c r receiver error 0 qcrc ccrc unlock v conf bip par 0d r interrupt status 0 pcch oslip detc cch rerr qch fch 0e r q-channel subcode [0:7] control control control control address address address address 0f r q-channel subcode [8:15] track track track track track track track track 10 r q-channel subcode [16:23] index index index index index index index index 11 r q-channel subcode [24:31] minute minute minute minute minute minute minute minute 12 r q-channel subcode [32:39] second second second second second second second second 13 r q-channel subcode [40:47] frame frame frame frame frame frame frame frame 14 r q-channel subcode [48:55] zero zero zero zero zero zero zero zero 15 r q-channel subcode [56:63] abs minute abs minute abs minute abs minute abs minute abs minute abs minute abs minute 16 r [q-channel subcode 64:71] abs second abs second abs second abs second abs second abs second abs second abs second 17 r q-channel subcode [72:79] abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame 18 r omck_rmck ratio orr7 orr6 orr5 orr4 orr3 orr2 orr1 orr0 19 r channel a status ac0[7] ac0[6] ac0[5] ac0[4] ac0[3] ac0[2] ac0[1] ac0[0] 1a r channel a status ac1[7] ac1[6] ac1[5] ac1[4] ac1[3] ac1[2] ac1[1] ac1[0] 1b r channel a status ac2[7] ac2[6] ac2[5] ac2[4] ac2[3] ac2[2] ac2[1] ac2[0] 1c r channel a status ac3[7] ac3[6] ac3[5] ac3[4] ac3[3] ac3[2] ac3[1] ac3[0] 1d r channel a status ac4[7] ac4[6] ac4[5] ac4[4] ac4[3] ac4[2] ac4[1] ac4[0]
36 ds578f3 cs8416 14. control port register descriptions 14.1 memory address pointer (map) not a register map[6:0] - memory address poin ter. will automatically incremen t after each read or write. default = ?0000000? 14.2 control0 (00h) fswclk ? forces the clock signal on omck to be output on rmck regardless of the swclk (control1 register bit 6) bit functionality or pll lock. default = ?0? 0 ? clock signal on omck is output on rmck according to the swclk bit functionality. 1 ? forces the clock signal on omck to be output on rmck regardless of the swclk bit functionality. pdur ? changes the type of phase detector used to lock to the active rxp[7:0] input. this bit should only be set if the sample rate range is between 32 khz and 108 khz. if the sample rate is outside of this range and the pdur bit is set, loss of lock may occur. default = ?0? 0 ? normal update rate phase dete ctor - recovered master clock (r mck) will have lo w wide-band jitter, but increased in-band jitter. 1e r channel b status bc0[7] bc0[6] bc0[5] bc0[4] bc0[3] bc0[2] bc0[1] bc0[0] 1f r channel b status bc1[7] bc1[6] bc1[5] bc1[4] bc1[3] bc1[2] bc1[1] bc1[0] 20 r channel b status bc2[7] bc2[6] bc2[5] bc2[4] bc2[3] bc2[2] bc2[1] bc2[0] 21 r channel b status bc3[7] bc3[6] bc3[5] bc3[4] bc3[3] bc3[2] bc3[1] bc3[0] 22 r channel b status bc4[7] bc4[6] bc4[5] bc4[4] bc4[3] bc4[2] bc4[1] bc4[0] 23 r burst preamble pc byte 0 pc0[7] pc0[6] pc0[5] pc0[4] pc0[3] pc0[2] pc0[1] pc0[0] 24 r burst preamble pc byte 1 pc1[7] pc1[6] pc1[5] pc1[4] pc1[3] pc1[2] pc1[1] pc1[0] 25 r burst preamble pd byte 0 pd0[7] pd0[6] pd0[5] pd0[4] pd0[3] pd0[2] pd0[1] pd0[0] 26 r burst preamble pd byte 1 pd1[7] pd1[6] pd1[5] pd1[4] pd1[3] pd1[2] pd1[1] pd1[0] 7f r id & version id3 id2 id1 id0 ver3 ver2 ver1 ver0 76543210 0 map6map5map4map3map2map1map0 76543210 0 fswclk 0 0 pdur trunc reserved reserved addr (hex) r/wfunction76543210
ds578f3 37 cs8416 1 ? higher update rate phase detector - recovered mast er clock (rmck) will have low in-band jitter, but increased wide-band jitter. use this setting for the best performance when the output is connected to a delta- sigma digital-to-analog converter (dac). trunc ? determines if the audio word length is set ac cording to the incoming channel status data as de- coded by the aux[3:0] bits. the resulting wo rd length in bits is 24 minus aux[3:0]. default = ?0? 0 ? incoming data is not truncated. 1 ? incoming data is truncated according to th e length specified in the channel status data. truncation occurs before the de-emphasis filter. trunc has no effect on output data if de-emphasis filter is not used. reserved ? these bits may change state depending on the input audio data. 14.3 control1 (01h) swclk - lets omck determine rmck, osclk, olrck when pll loses lock default = ?0? 0 - disable automatic clock switching. rmck runs at the vco frequency (~750 khz) on pll unlock. 1 - enable automatic clock switching on pll unlock. omck clock input is automatically output on rmck on pll unlock. mutesao - mute control for the serial audio output port default = ?0? 0 - sdout not muted. 1 ? sdout muted (set to all zeros). int[1:0] - interrupt output pin (int) control default = ?00? 00 - active high; high output indicates interrupt condition has occurred. 01 - active low, low output indicates an interrupt condition has occurred. 10 - open drain, active low. requires an external pull- up resistor on the int pin. thus it is not recommended to multiplex int onto gpo2 in i2c control port mode since an external resistor is required on gpo2 to spec- ify the ad2 bit of the chip address. 11 ? reserved. hold[1:0] ? determine how received aud io sample is affected wh en a receive error occurs default = ?00? 00 ? hold last audio sample. 01 ? replace the current audio sa mple with all zeros (mute). 10- do not change the received audio sample. 11 - reserved 76543210 swclk mutesao int1 int0 hold1 hold0 rmckf chs
38 ds578f3 cs8416 rmckf ? recovered master clock frequency default = ?0? 0 ? rmck output frequency is 256*f s . 1 ? rmck output frequency is 128*f s . chs ? sets which channel's c data is decoded in the receiver channel st atus register (0ah). default = ?0? 0 ? a channel. 1 ? b channel. if chs = 0 and trunc = 1, both channel s' audio data will be truncated by the aux[3:0] bits indicated in the channel a channel status data. if chs = 1 and trunc = 1, both channels ' audio data will be truncated by the aux[3:0] bits indicated in the channel b channel st atus data. this w ill occur even if the aux[3:0] bits indicated in the channel a channel status data are no t equal to the aux[3:0] bits indicated in the channel b channel status data. 14.4 control2 (02h) detci ? d to e status transfer inhibit default = ?0? 0 ? allow update. 1 ? inhibit update. emph_cntl[2:0] ? de-emphasis filter control. see figure 14 for de-emphasis filter response. default = ?000? 000 ? if the serial audio output port is using the aes3 direct-output format, the de-emphasis filter must re- main off. 001 ? 32 khz setting. 010 ? 44.1 khz setting. 011 ? 48 khz setting. 100 ? 50 s/15 s de-emphasis filter auto-select on. coefficient s (32, 44.1 or 48 khz or no de-emphasis fil- ter at all) match the pre-emphasis and sample frequency indicators in the channel status bits of channel a. thus it is impossible to have de-emphasis applied to one channel but not the other. the de-emphasis filter is turned off if the audio data is detected to be non-audio data. gpo0sel[3:0] ? gpo0 source select. see ?general purpose outputs? on page 29 . default = ?0000? 76543210 detci emph_cntl2 emph_cntl1 emph_cntl0 gpo0sel3 gpo0sel2 g po0sel1 gpo0sel0
ds578f3 39 cs8416 14.5 control3 (03h) gpo1sel[3:0] ? gpo1 source select. see ?general purpose outputs? on page 29 . default = ?0000? gpo2sel[3:0] ? gpo2 source select. see ?general purpose outputs? on page 29 . default = ?0000? 14.6 control4 (04h) run - controls the internal clocks, allowing the cs8416 to be placed in a ?powered down?, low current con- sumption state. default = ?0? 0 - internal clocks are stopped. internal state ma chines are reset. the fully static control port is operational, allowing registers to be read or changed. power consumption is low. 1 - normal part operation. this bit mu st be written to the 1 state to allo w the cs8416 to begin operation. all input clocks should be stable in fr equency and phase w hen run is set to 1. rxd ? rmck control default = ?0? 0 -rmck is an output, clock is derived from input frame rate. 1 ? rmck becomes high impedance. the output of osclk, olrck, and sdout are indeterminate. rx_sel[2:0] ? selects rxp0 to rxp7 for input to the receiver default =?000? 000 ? rxp0 001 ? rxp1, etc 7 6 543210 gpo1sel3 gpo1sel2 gpo1sel1 gpo1sel0 g po2sel3 gpo2sel2 gpo2sel1 gpo2sel0 76543210 run rxd rxsel2 rxsel1 rxsel0 txsel2 txsel1 txsel0 figure 14. de-emphasis filter response f2 f1 -10 3.183 frequency, khz t1 = 50us 0 10.61 gain, db t2 =15us
40 ds578f3 cs8416 tx_sel[2:0] ? selects rxp0 to rxp7 as the input for gpo tx source default =?001? 000 ? rxp0 001 ? rxp1, etc 14.7 serial audio data format (05h) soms - master/slave mode selector default = ?0? 0 - serial audio output port is in sl ave mode. osclk and olrck are inputs. 1 - serial audio output port is in master mode. osclk and olrck are outputs. sosf - osclk frequency (for master mode) default = ?0? 0 - osclk output frequency is 64*f s . 1 - osclk output frequency is 128*f s . sores[1:0] - resolution of the output data on sdout default = ?00? 00 - 24-bit resolution. 01 - 20-bit resolution. 10 - 16-bit resolution. 11 - direct copy of the received nrz data from the aes3 receiver incl uding c, u, and v bits. the time slot occupied by the z bit is used to indicate the location of the block start. this setting forces the sojust bit to be ?0?. when using this setting, the de-emphasis filter must be off. sojust - justification of sdout data relative to olrck default = ?0? 0 - left-justified. 1 - right-justified (master mode only and sores 11). sodel - delay of sdout data relative to olrck, for left-justified data formats (this control is only valid in left-justified mode) default = ?0? 0 - msb of sdout data occurs in the first osclk period after the olrck edge. 1 - msb of sdout data occurs in the second osclk period after the olrck edge. sospol - osclk clock polarity default = ?0? 0 - sdout is sampled on rising edges of osclk. 1 - sdout is sampled on falling edges of osclk. 76543210 soms sosf sores1 sores0 sojust sodel sospol solrpol
ds578f3 41 cs8416 solrpol - olrck clock polarity default = ?0? 0 - sdout data is valid for the le ft channel when olrck is high. 1 - sdout data is valid for the ri ght channel when olrck is high. 14.8 receiver error mask (06h) the bits in this register serve as masks for the corresponding bits of the receiver error register. if a mask bit is set to 1, the error is unmask ed, meaning that its occurrence will app ear in the receiver error register, will affect rerr, will affect the rerr interrupt, and w ill affect the curr ent audio sample according to the status of the hold bit. if a mask bit is set to 0, the error is masked, meaning that its occu rrence will not appear in the receiver error register , will not affect the rerr pin, will not affect the rerr interrupt, and will not affect the current audio sample. the ccrc and qcrc bits behave differently from the other bits: they do not affect the current audio sample even wh en unmasked. this register defaults to 00h. 14.9 interrupt mask (07h) the bits of this register se rve as a mask for the interrupt status register. if a mask bit is set to 1, the error is unmasked, meaning that its occurr ence will affect the int pin and the status register. if a mask bit is set to 0, the error is masked, meaning th at its occurrence will not affect the internal int signal or the status reg- ister. the bit positions align with the corresponding bits in interrupt status register. this register defaults to 00h. the int signal may be selected to output on the gpo pins. see ?general purpose outputs? on page 29 . 14.10 interrupt mode msb (08h) and interrupt mode lsb(09h) the two interrupt mode registers form a 2-bit code for each interrupt status regi ster function. there are three ways to set the int pin active in accordance with the interrupt condition. in the rising edge active mode, the int pin becomes active on the arrival of the interrupt condit ion. in the falling edge active mode, the int pin becomes active on the removal of the interr upt condition. in level active mode, the int interrupt pin becomes active during the interrupt condition. be aware that the active level (active high or low) only depends on the int[1:0] bits. these registers default to 00h. 00 - rising edge active 01 - falling edge active 10 - level active 11 - reserved 76543210 0 qcrcm ccrcm unlockm vm confm bipm parm 76543210 0 pcchm oslipm detcm cchm rerrm qchm fchm 76543210 0 pcch1 oslip1 detc1 cch1 rerr1 qch1 fch1 0 pcch0 oslip0 detc0 cch0 rerr0 qch0 fch0
42 ds578f3 cs8416 14.11 receiver channel status (0ah) the bits in this register can be associated with either channel a or b of the received data. the desired chan- nel is selected with the chs bit of the control1 register. aux3:0 - incoming auxiliary data field width, as indicate d by the incoming channel status bits, decoded ac- cording to iec60958 and aes3. 0000 - auxiliary da ta is no t present. 0001 - auxiliary da ta is 1 bit long. 0010 - auxiliary data is 2 bits long. 0011 - auxiliary data is 3 bits long. 0100 - auxiliary data is 4 bits long. 0101 - auxiliary data is 5 bits long. 0110 - auxiliary data is 6 bits long. 0111 - auxiliary data is 7 bits long. 1000 - auxiliary data is 8 bits long. 1001 - 1111 reserved pro - channel status block format indicator 0 - received channel status block is in the consumer format. 1 - received channel status block is in the professional format. copy - scms copyright indicator 0 - copyright asserted. 1 - copyright not asserted. if the category code is set to general in the incoming aes3 stream, copyright will always be indicated by copy, even when the stream indicates no copyright. orig - scms generation indicator, decoded from the category code and the l bit. 0 - received data is 1st generation or higher. 1 - received data is original. note: copy and orig will both be set to 1 if incoming data is flagged as professional or if the receiver is not in use. emph ? indicates whether the input audio data has been pre-emphasized. also indicates turning on of the de-emphasis filter during de-emphasis auto-select mode. 0 ? 50 s/15 s pre-emphasis indicated. 1 ? 50 s/15 s pre-emphasis not indicated. 14.12 format detect status (0bh) note: pcm, dts_ld, dts_cd and iec61937 are mutually exclusive. a ?1? indicated the condition was detected. pcm ? uncompressed pcm data was detected. iec61937 ? iec61937 data was detected. dts_ld ? dts_ld data was detected. 76543210 aux3 aux2 aux1 aux0 pro copy orig emph 76543210 0 pcm iec61937 dts_ld dts_cd reserved dgtl_sil 96khz
ds578f3 43 cs8416 dts_cd ? dts_cd data was detected. reserved ? this bit may change state depending on the input audio data. dgtl_sil ? digital silence was detected: at least 2047 co nsecutive constant samples of the same 24-bit audio data on both channels. 96khz ? if the input sample rate is 48 khz, outputs a ?0?. outputs a ?1? if the sample rate is 88.1 khz. otherwise the output is indeterminate. 14.13 receiver error (0ch) this register contains th e aes3 receiver and pll status bits. un masked bits will go high on occurrence of the error, and will st ay high until the register is re ad. reading the register resets a ll bits to 0, unless the error source is still true. bits that are mask ed off in the receiver er ror mask register will always be 0 in this register. qcrc - q-subcode data crc error indicator. updated on q-subcode block boundaries 0 - no error. 1 - error. ccrc - channel status block cyclic redundancy check bit. updated on cs block boundaries, valid in pro mode 0 - no error. 1 - error. unlock - pll lock status bit. updated on cs block boundaries. 0 - pll locked. 1 - pll out of lock. v - received aes3 validity bit status . updated on sub-frame boundaries. 0 - data is valid and is normally linear coded pcm audio. 1 - data is invalid, or ma y be valid compressed audio. conf - confidence bit. updated on sub-frame boundaries. 0 - no error. 1 - confidence error. the logical or of unlock and bip. the input data stream may be near error condi- tion due to jitter degradation. bip - bi-phase error bit. updated on sub-frame boundaries. 0 - no error. 1 - bi-phase error. this indicates an error in the received bi-phase coding. par - parity bit. updated on sub-frame boundaries. 0 - no error. 1 - parity error. 76543210 0 qcrc ccrc unlock v conf bip par
44 ds578f3 cs8416 14.14 interrupt 1 status (0dh) for all bits in this regist er, a ?1? means the associated interrupt cond ition has occurred at least once since the register was last read. a ?0? means the associated interrupt condition has not occurred since the last reading of the register. readi ng the register resets all bits to 0, unle ss the interrupt mode is set to level and the interrupt source is still true. st atus bits that are mask ed off in the associated mask register will always be ?0? in this register. pcch ? pc burst preamble change. indicates that the pc byte has changed from its previ ous value. if the iec61937 bit in the format detect status register goes high, it will cause a pcch inte rrupt even if the pc byte ha sn?t changed since the last time the iec61937 bit went high. oslip - serial audio output port data slip interrupt when the serial audio output port is in slave mode , and olrck is asynchronous to the port data source, this bit will go high ever y time a data sample is dropped or r epeated. see ?slip/repeat behavior? on page 25 for more information. detc - d to e c-buffer transfer interrupt. indicates the completion of a d to e c-buffer transfer. see ?channel status buffer management? on page 51 . c_change -indicates that the current 10 bytes of channel status is different from the previous 10 bytes. (5 bytes per channel) rerr - a receiver error has occurred. the receiver error register may be read to determine the nature of the error which caused the interrupt. qch ? a new block of q-subcode is available for readin g. the data must be read within 588 aes3 frames after the interrupt occurs to avoid corruption of the data by the next block. fch ? format change: goes high when the pcm, iec61937, dts_ld, dts_cd, or dgtl_sil bits in the format detect status register transition from 0 to 1. when these bits in the format detect status register transition from 1 to 0, an in terrupt will not be gene rated. 14.15 q-channel subcode (0eh - 17h) each byte is lsb first with respect to the 80 q-subcode bits q[79:0]. thus, bit 7 of address 0eh is q[0] while bit 0 of address 0eh is q[7]. similarly, bit 0 of address 17h corresponds to q[79]. 76543210 0 pcch oslip detc cch rerr qch fch 76543210 control control control contr ol address address address address track track track track track track track track index index index index index index index index minute minute minute minute m inute minute minute minute second second second second second second second second frame frame frame frame frame frame frame frame zero zero zero zero zero zero zero zero abs minute abs minute abs minute abs minute ab s minute abs minute abs minute abs minute abs second abs second abs second abs second abs second abs second abs second abs second abs frame abs frame abs frame abs frame abs frame abs frame abs frame abs frame
ds578f3 45 cs8416 14.16 omck/rmck ratio (18h) this register allows the calculation of the incoming sample rate by the host microcontroller from the equation orr=fso/fsi. the fso is determined by omck, whos e frequency is assumed to be 256*fso. orr is rep- resented as an unsigned 2-bit integer and a 6-bit fracti onal part. the value is meaningful only after the pll has reached lock. for example, if the omck is 12.288 mhz, fso would be 48 khz (48 khz = 12.288 mhz/256). then, if the input sample rate is al so 48 khz, you would get 1.0 from the orr register (the value from the orr regist er is hexadecimal, so the ac tual value you will get is 40h). if f so /f si > 3 63 / 64 , orr will saturate at the value ffh. also, th ere is no hyst eresis on orr. therefore a small amount of jitter on either clock can cause the lsb o rr[0] to oscillate. orr[7:6] - integer part of the ratio (integer value=integer(srr[7:6])). orr[5:0] - fractional part of the ratio (fraction value=integer(srr[5:0])/64). 14.17 channel status re gisters (19h - 22h) 14.18 iec61937 pc/pd burst preamble (23h - 26h) 14.19 cs8416 i.d. and ve rsion register (7fh) id[3:0] - id code for the cs8416. permanently set to 0010 ver[3:0] = 0001 (revision a) ver[3:0] = 0010 (revision b) ver[3:0] = 0011 (revision c) ver[3:0 ] = 0111 (revision d) ver[3:0] = 1111 (revision e) 76543210 orr7 orr6 orr5 orr4 orr3 orr2 orr1 orr0 19h channel a status byte 0 ac0[7] ac0[6] ac0[5] ac0[4] ac0[3] ac0[2] ac0[1] ac0[0] 1ah channel a status byte 1 ac1[7] ac1[6] ac1[5] ac1[4] ac1[3] ac1[2] ac1[1] ac1[0] 1bh channel a status byte 2 ac2[7] ac2[6] ac2[5] ac2[4] ac2[3] ac2[2] ac2[1] ac2[0] 1ch channel a status byte 3 ac3[7] ac3[6] ac3[5] ac3[4] ac3[3] ac3[2] ac3[1] ac3[0] 1dh channel a status byte 4 ac4[7] ac4[6] ac4[5] ac4[4] ac4[3] ac4[2] ac4[1] ac4[0] 1eh channel b status byte 0 bc0[7] bc0[6] bc0[5] bc0[4] bc0[3] bc0[2] bc0[1] bc0[0] 1fh channel b status byte 1 bc1[7] bc1[6] bc1[5] bc1[4] bc1[3] bc1[2] bc1[1] bc1[0] 20h channel b status byte 2 bc2[7] bc2[6] bc2[5] bc2[4] bc2[3] bc2[2] bc2[1] bc2[0] 21h channel b status byte 3 bc3[7] bc3[6] bc3[5] bc3[4] bc3[3] bc3[2] bc3[1] bc3[0] 22h channel b status byte 4 bc4[7] bc4[6] bc4[5] bc4[4] bc4[3] bc4[2] bc4[1] bc4[0] 23h burst preamble pc byte 0 pc0[7] pc0[6 ] pc0[5] pc0[4] pc0[3] pc0[2] pc0[1] pc0[0] 24h burst preamble pc byte 1 pc1[7] pc1[6 ] pc1[5] pc0[4] pc1[3] pc1[2] pc1[1] pc1[0] 25h burst preamble pd byte 0 pd0[7] pd0[6 ] pd0[5] pc0[4] pd0[3] pd0[2] pd0[1] pd0[0] 26h burst preamble pd byte 1 pd1[7] pd1[6 ] pd1[5] pd1[4] pd1[3] pd1[2] pd1[1] pd1[0] 76543210 id3 id2 id1 id0 ver3 ver2 ver1 ver0
46 ds578f3 cs8416 15.hardware mode the cs8416 has a hardware mode that allows the device to operate without a microcontroller. hardware mode is selected by connecting the 47 k pull-up/down resistor on the sdout pin to ground. various pins change function in hardware mode, described in section 15.2 ?hardware mode fu nction selection? on page 46 . hardware mode data flow is shown in figure 15 . audio data is input through th e aes3/spdif receiver, and routed to the serial audio output port. the decoded c and u bits are also output, clocked at both edges of olrck (master mode only, see figure 10 ). an error in the incoming audio stream will be indicated on the nv /rerr pin. this pin can be configured in one of two ways. if rerr is chosen by pulling nv/rerr to vl, th e previous audio sample is held and passed to the serial audio output port if the validity bit is high, or a parity, bi -phase, confidence or pll lock error occurs during the current sample. if nverr is chosen by pulling nv/rerr to dgnd, on ly parity, bi-phase, confidence or pll lock error cause the previous audio sample to be held. 15.1 serial audio port formats in hardware mode, only a limited number of alte rnative serial audio port formats are available. table 5 de- fines the equivalent software mode bit settings for each format. the start-up options, shown in table 4 , allow choice of the serial audio outp ut port as a master or slave, and the serial audio po rt format. 15.2 hardware mode function selection hardware mode and several options for hardwa re mode are selected by pulling cs8416 pins up to vl or down to dgnd through a 47 k resistor. these settings are sensed immediately after rst is released. for nv/rerr power supply pins (va, vd, and vl), agnd, dgnd, the reset pin (rst) and the pll filter pin (filt) are omitted from the diagram. please refer to the typical connection diagram for connection details. rxp1 4:2 mux rxp2 rxp3 rxp0 96khz rmck rxsel[1:0] txsel[1:0] audio rcbl rxn aes3 rx & decoder omck tx olrck osclk sdout c u de-emphasis filter serial audio output tx passthrough figure 15. hardware mode data flow
ds578f3 47 cs8416 each mode, every start-up option select pin (except for tx, which has an internal pull-down) must have an external pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup conditions (set after reset). 15.3 hardware mode equival ent register settings listed below are the equivalent values that the registers are set to in hardware mode. control0 register (00h) fswclk = 0 pdur = set by tx pin pull-up/down after reset. trunc = 0 control1 register (01h) swclk = set to 1 if there a transition on omck after reset. otherwise set to 0. mutsao = 0 int[1:0] = n/a. hold[1:0] = 00 rmckf = set by u pin pull-up/down after reset. chs = 0 control2 register (02h) detci = n/a emph_cntl[2] = set by 96khz pull-up/down after reset. see figure 14 for the de-emphasis filter re- sponse. emph_cntl[1:0] = 00 gpo0sel[3:0] = n/a control3 register (03h) gpo1sel[3:0] = n/a gpo2sel[3:0] = n/a pin name pull down to dgnd fun ction pull up to vl function sdout hardware mode software mode rcbl serial port slave mode serial port master mode audio serial format select 1 (sfsel1) =0 serial format select 1 (sfsel1)=1 c serial format select 0 (sfsel0)=0 serial format select 0 (sfsel0)=1 u rmck frequency=256*f s rmck frequency=128*f s tx normal phase detector update rate. higher phase detector update rate. 96khz emphasis audio match off emphasis audio match on nv/rerr nverr selected rerr selected table 4. hardware mode start-up pin conditions
48 ds578f3 cs8416 control4 register (04h) run = 1 rxd = 0 rx_sel[2] = 0 rx_sel[1:0] = rx_sel[1:0] pins. tx_sel[2] = 0 tx_sel[1:0] = tx_sel[1:0] pins. serial audio data format register (05h) soms = set by rcbl pull-up/down after reset. bits[6:0] = set by pull-up/down on audio & c after reset. see table 5 for bit settings. receiver error mask register (06h) qcrcm = 0 crcm = 0 unlockm = 1 confm = 1 bipm = 1 parm = 1 vm = set by nv/rerr pull-up/down after reset. registers 07h through 7fh do not have hardware mode equivalent settings. serial format select [1:0] sosf s ores[1:0] sojust sodel sospol solrpol 00 (left-justified 24-bit) 0 00 0 0 0 0 01(i2s 24 bit) 0 00 0 1 0 1 10 (right-justified 24-bit) 0 00 1 0 0 0 11 (direct aes3) 0 11 0 0 0 0 table 5. hardware mode serial audio format select
ds578f3 49 cs8416 16.external aes3/spdif/iec60 958 receiver components 16.1 aes3 receiver ex ternal components the cs8416 aes3 receiver is designed to accept both the professional and consumer interfaces. the dig- ital audio specifications for professional use ca ll for a balanced receiver, using xlr connectors, with 110 20% impedance. the xlr connector on the receiver should have female pins with a male shell. since the receiver has a very high input impedance, a 110 resistor should be placed across the receiver terminals to match the line impedance, as shown in figures 16 and 17 . although transformers are not re- quired by the aes specification, they are strongly recommended. if some isolation is desired with out the use of transformers, a 0.01 f capacitor should be placed in series with each input pin (rxp[7:0] and rxn) as shown in figure 17 . however, if a transformer is not used, high frequency energy could be coupled into the re ceiver, causing degradation in analog performance. figures 16 and 17 show an optional (recommen ded) dc blocking capacitor (0.1 f to 0.47 f) in series with the cable input. this improves the robustness of the re ceiver, preventing the satu ration of the transformer, or any dc current flow, if a dc voltage is present on the cable. in the case of the consumer interface, the standards call for an unbalanced circuit having a receiver imped- ance of 75 5%. the connector for the consumer interface is an rca phono socket. the receiver circuit for the consumer inte rface is shown in figure 18 . an implementation of the input s/pdif multiplexer using the consumer interf ace is shown in figure 19 . the circuit shown in figure 20 may be used when external rs422 re ceivers, optical receivers or other ttl/cmos logic outputs drive the cs8416 receiver section. in the configuration of systems, it is important to avoid ground loops and dc current flowing down the shield of the cable that could result when boxes with diffe rent ground potentials are connected. generally, it is good practice to ground the shield to the chassis of the transmitting unit, and connect the shield through a capacitor to chassis ground at the receiver. however, in some cases it is advantageous to have the ground of two boxes held to the same potential, and the cable shield might be depended upon to make that electrical connection. generally, it is a good idea to provide the option of grounding or capacitively coupling the shield to the chassis. 16.2 isolating transformer requirements please refer to the application note an134: aes and spdif recomm ended transformers for resources on transformer selection. 1 xlr twisted pair 110 110 cs8416 rxp0 rxn * see text 1 xlr twisted pair 110 110 cs841 6 rxp0 rxn 0.01 f 0.01 f *seetext figure 16. professional input circuit figure 17. transformerless prof essional input circuit
50 ds578f3 cs8416 rxp7 rxn rxp0 rxp6 75 .01 f .01 f .01 f . . . .01 f 75 coax 75 75 75 coax 75 coax cs8416 figure 18. consumer input circuit fi gure 19. s/pdif mux input circuit rca phono rxp0 rxn cs8416 coax 75 75 0.01 f 0.01 f rxp0 rxn cs8416 0.01 f 0.01 f ttl/cmos gate figure 20. ttl/cmos input circuit
ds578f3 51 cs8416 17.channel status buffer management 17.1 aes3 channel status (c) bit management the cs8416 contains sufficient ram to store the first 5 bytes of c data for both a and b channels (5 x 2 x 8 = 80 bits). the user may read from this buffer?s ram through the control port. the buffering scheme involves two buffers, named d and e, as shown in figure 21 . the msb of each byte represents the first bit in the serial c data stream. for example, the msb of byte 0 (which is at control port address 19h) is the consumer/profess ional bit for channel status block a. the first buffer (d) accepts incoming c data from the aes receiver. the 2nd buffer (e) accepts entire blocks of data from the d buffer. the e buffer is also accessibl e from the control port, allowing reading of the first five bytes of c data. the complete c data may be obtained through the c pin in hardware mode and through one of the gpo pins in software mode. the c data is serially shifted out of the cs8416 clocked by the rising and falling edges of olrck. 17.2 accessing the e buffer the user can monitor the incoming data by reading the e buffer, which is mapped into the register space of the cs8416, through the control port. the user can configure the interrupt enable register to cause interrupts to occur whenever d to e buffer transfers occur. this allows determination of the a llowable time periods to interact with the e buffer. also provided is a d to e inhibit bit in the control2 re gister (02h). this may be us ed whenever ?long? control port interactions are occurri ng or for debugging purposes. a flowchart for reading the e buffer is shown in figure 22 . since a d to e interrupt occurs just after reading, there is a substantial time interval until the next d to e transfer (appro ximately 192 frames worth of time). this is usually enough time to access the e da ta without having to inhibit the next transfer. 17.2.1 serial copy mana gement system (scms) in software mode, the cs8416 allows read access to all the channel status bits. for consumer mode scms compliance, the host microcontroller needs to read and interpret the category code, copy bit and l bit appropriately. in hardware mode, the scms protocol can be followed by either using the copy and orig output pins, or by using the c bit serial output pin. these options are documented in section 15. ?hardware mode? on page 46 .
52 ds578f3 cs8416 control port registers from aes3 receiver e 19 words 8-bits 8-bits ab d received data buffer 5 words c data serial output figure 21. channel status data buffer structure d to e interrupt occurs optionally set d to e inhibit read e data if set, clear d to e inhibit return figure 22. flowchart for reading the e buffer
ds578f3 53 cs8416 18.pll filter 18.1 general an on-chip phase locked loop (pll) is used to recover the clock from the incoming data stream. figure 23 is a simplified diagram of the pll. when the pll is lock ed to an bi-phase encoded input stream, it is updat- ed at each preamble in the bi-phase encoded stre am. this occurs at twice the sampling frequency, f s . there are some applications where low jitter in the re covered clock, presented on the rmck pin, is impor- tant. for this reason, the pll has been designed to ha ve good jitter attenuation characteristics, as shown in figure 25 . in addition, the pll has been designed to onl y use the preambles (pdu r=0) of the bi-phase encoded stream to provide lock update information to the pll. this results in the pll being immune to data dependent jitter affects because the preambles do not vary with the data. the pll has the ability to lock onto a wide range of input sample rates with no ex ternal compo nent changes. if the sample rate of the input subsequently change s, for example in a varispeed application, the pll will only track up to 12.5% from the nominal center sample rate. the nominal center sample rate is the sample rate that the pll first locks onto upon application of an bi-phase encoded data stream or after enabling the cs8416 clocks by setting the run c ontrol bit. if the 12.5% sample rate limit is exceeded, the pll will return to its wide lock range mode and re-acquire a new nominal center sample rate. 18.2 external filter components 18.2.1 general the pll behavior is affected by the external filter component values. figures 5 and 6 shows the recom- mended configuration of the two capacitors and one resistor that comprise the pll filter. in table 6 , the component values shown have a high corner frequency jit ter attenuation curve, take a short time to lock, and offer good output jitter performance. lock time s are worst case for an fsi transition of 192 khz. it is important to treat the pll flt pin as a low-level analog input. it is suggested that the ground end of the pll filter be returned directly to the agnd pin independently of the ground plane. phase comparator and charge pump n vco rmck input c rip c flt r flt figure 23. pll block diagram
54 ds578f3 cs8416 18.2.2 capacitor selection the type of capacitors used for the pll filter can have a significant ef fect on receiver performance. large or exotic film capacitors are not nec essary as their leads and the required longer circuit board traces add undesirable inductance to the circuit. surface mount ceramic capacitors are a good choice because their own inductance is low, and they can be mounted close to the filt pin to minimize trace inductance. for c rip , a c0g or npo dielectric is recommended, and for c flt , an x7r dielectric is preferred. avoid ca- pacitors with large temperature co-coefficient, or capac itors with high dielectric constants, that are sensi- tive to shock and vibration. these include the z5u and y5v dielectrics. 18.2.3 circuit board layout board layout and capacitor choice affect each ot her and determine the performance of the pll. figure 24 contains a suggested layout for the pll filter components and for bypassing the analog supply voltage. the 0.1 f bypass capacitor is in a 1206 form factor. r flt , c flt , c rip , and the 1000 pf decoupling ca- pacitor are in an 0805 form factor. the traces are on th e top surface of the board with the ic so that there is no via inductance. the traces themselves are shor t to minimize the inductance in the filter path. the va and agnd traces extend back to their origin and are shown only in truncated form in the drawing. 18.2.4 component value selection the external pll component values are listed in table 6 . range (khz) r flt c flt c rip settling time 32 - 192 3 k 22 nf 1 nf 4 ms table 6. external pll component values va agnd filt c flt 1000 pf .1f r flt c rip figure 24. recommended layout example
ds578f3 55 cs8416 18.2.5 jitter attenuation shown in figure 25 is the jitter attenuation plot. the aes3 and iec60958-4 specifications state a maxi- mum of 2 db jitter gain or peaking. 10 1 10 0 10 1 10 2 10 3 10 4 10 5 12 10 8 6 4 2 0 2 4 j itte r f re que nc y ( h z ) e xte rna l j itte r a tte nua tion ( db ) figure 25. jitter attenuation characteristics of pll
56 ds578f3 cs8416 19.package dimensions inches millimeters dim min nom max min nom max a 0.093 0.098 0.104 2.35 2.50 2.65 a1 0.004 0.008 0.012 0.10 0.20 0.30 b 0.013 0.017 0.020 0.33 0.42 0.51 c 0.009 0.011 0.013 0.23 0.28 0.32 d 0.697 0.705 0.713 17.70 17.90 18.10 e 0.291 0.295 0.299 7.40 7.50 7.60 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.394 0.407 0.419 10.00 10.34 10.65 l 0.016 0.026 0.050 0.40 0.65 1.27 0 4 8 0 4 8 jedec #: ms-013 controlling dimensi on is millimeters 28l soic (300 mil body) package drawing d h e b a1 a c l seating plane 1 e
ds578f3 57 cs8416 notes: 1. ?d? and ?e1? are reference datums and do not includ e mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/ intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not re- duce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. tssop thermal characteristics inches millimeters note dim min nom max min nom max a -- --0.47-- --1.20 a1 0.002 0.004 0.006 0.05 0.10 0.15 a2 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2 , 3 d 0.378 bsc 0.382 bsc 0.386 bsc 9.60 bsc 9.70 bsc 9.80 bsc 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- 0.026 bsc -- -- 0.65 bsc -- l 0.020 0.024 0.029 0.50 0.60 0.75 0 4 8 0 4 8 jedec #: mo-153 controlling dimension is millimeters. parameter symbol min typ max units junction to ambient thermal impedance 4 layer board ja - 40 -c/watt 28l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
58 ds578f3 cs8416 28-pin qfn (5 5 mm body) package drawing notes: 1. dimensioning and tolerance per asme y 14.5m-1995. 2. dimensioning lead width applies to the plated te rminal and is measured between 0.23mm and 0.28mm from the terminal tip. qfn thermal characteristics inches millimeters note dim min nom max min nom max a -- -- 0.0394 -- -- 1.00 1 a1 0.0000 -- 0.0020 0.00 -- 0.05 1 b 0.0071 0.0091 0.0118 0.18 0.23 0.30 1 , 2 d 0.1969 bsc 5.00 bsc 1 d2 0.1220 0.1240 0.1260 3.10 3.15 3.20 1 e 0.1969 bsc 5.00 bsc 1 e2 0.1220 0.1240 0.1260 3.10 3.15 3.20 1 e 0.0197 bsc 0.50 bsc 1 l 0.0197 0.0236 0.0276 0.50 0.60 0.70 1 jedec #: mo-220 controlling dimension is millimeters. parameter symbol min typ max units junction to ambient thermal impedance 2 layer board 4 layer board ja - - 130 37 - - c/watt c/watt side view a a1 d2 l b e pin #1 corner bottom view top view pin #1 corner d e e2
ds578f3 59 cs8416 20.ordering information product description pb-free grade temp range package container order# cs8416 192 khz digital audio interface receiver yes commercial -10 to +70 c 28-soic rail cs8416-csz tape and reel cs8416-cszr 28-tssop rail cs8416-czz tape and reel cs8416-czzr 28-qfn rail cs8416-cnz tape and reel cs8416-cnzr automotive -40 to +85 c 28-soic rail cs8416-dsz tape and reel cs8416-dszr 28-tssop rail cs8416-dzz tape and reel cs8416-dzzr 28-qfn rail CS8416-DNZ tape and reel CS8416-DNZr cdb8416 evaluation board for cs8416 - - - - - cdb8416
60 ds578f3 cs8416 21.revision history release changes f1 -reformatted ?features? on page 1 -added rmck/omck maximum in ?switching characteristics? on page 8 . -corrected aes3 direct format in ?serial audio output example formats? on page 24 . -corrected table 2 and page 28 text referencing vco idle frequency. -added timing note to figure 10 on page 32 . -corrected ?control port description? on page 33 to reflect the auto-increment function of the map. -added thermal relief pad label to qfn package in ?pin description - software mode? on page 12 and ?pin description - hardware mode? on page 16 . -added ?tssop thermal characteristics? on page 57 and ?qfn thermal characteristics? on page 58 . f2 clarified use of de-emphasis filt er in aes3 direct-output format. f3 updated ordering information to include automotive grade qfn option. contacting cirrus logic support for all product questions and inquiries, c ontact a cirrus logic sales representative. to find the one nearest you, go to www.cirrus.com. important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warran ty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential ri sks of death, personal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in aircraft systems, military a pplications, products s urgically implanted into the body, automotive sa fety or security de- vices, life support products or other cri tical applications. inclus ion of cirrus products in s uch applications is under- stood to be fully at the customer?s risk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer uses or permits the use of cirrus products in critical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. ac-3 is a registered trademark of dolby laboratories, inc. dts is a registered trademark of the digital theater systems, inc. i2c is a registered trademark of philips semiconductor. spi is a trademark of motorola inc.

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